linux-kernel - Re: [PATCH 0/8] Enhance Winbond SPI NAND support

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Message-ID: <87v7nam46q.fsf@bootlin.com>
Date: Wed, 30 Jul 2025 11:13:49 +0200
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Mark Brown <broonie@...nel.org>
Cc: Richard Weinberger <richard@....at>,  Vignesh Raghavendra
 <vigneshr@...com>,  Yogesh S <yogeshs@...com>,  Santhosh Kumar K
 <s-k6@...com>,  Steam Lin <STLin2@...bond.com>,  Thomas Petazzoni
 <thomas.petazzoni@...tlin.com>,  linux-spi@...r.kernel.org,
  linux-kernel@...r.kernel.org,  linux-mtd@...ts.infradead.org
Subject: Re: [PATCH 0/8] Enhance Winbond SPI NAND support

Hello,

On 18/06/2025 at 14:14:17 +02, Miquel Raynal <miquel.raynal@...tlin.com> wrote:

> Both w25n**jw and w35n**jw chips have a "normal" and a "high speed"
> mode. In order to use the high speed modes, we need to configure
> internal registers and adapt the number of dummy cycles. The benefits
> are too interesting for not paying attention to this little extra
> configuration. In particular, it is an important building block for the
> introduction of PHY calibration on TI SPI controllers. With these
> changes combined, the frequency used on these chips can be bumped from
> ~25MHz up to 166MHz.
>
> This series was tested on TI AM62A SK with a W35N01JW and on Nuvoton
> MA35D with a W25N01JW. At low speeds, this series does not bring any
> improvement. However when enabling high speed modes (on TI's platform),
> the difference is outstanding:
>
> W35N*JW running in 1S-8S-8S @ 25MHz:
>
> 	 eraseblock read speed is 9552 KiB/s
> 	 page read speed is 9516 KiB/s
> 	 2 page read speed is 9552 KiB/s
>
> W35N*JW running in 1S-8S-8S @ 166MHz:
>
> 	eraseblock read speed is 35555 KiB/s
> 	page read speed is 33684 KiB/s
> 	2 page read speed is 35068 KiB/s
>
> Enabling high speeds currently requires applying extra patches from TI
> to enable PHY calibration. They are currently in the upstreaming process.
>
> Link: https://github.com/miquelraynal/linux/tree/winbond/6.16-rc1/octal-phy
>
> In order to introduce all these variants and derive the quickest one, I
> had to improve a bit the helper deriving the time an ops would
> take. These changes can go through the spi tree, the other patches do
> not depend on them and the performance hit is rather acceptable without.
>
> While at adding maximum operation frequencies, I realized I got myself
> confused with the macro parameters due to some of them being
> optional (with variable arguments in macros). I decided it was too error
> prone so I propose to add these values on all READ_FROM_CACHE
> variants (where they are often relevant).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
> ---
> Miquel Raynal (8):
>       spi: spi-mem: Use picoseconds for calculating the op durations
>       spi: spi-mem: Take into account the actual maximum frequency
>       mtd: spinand: Fix macro alignment
>       mtd: spinand: Add a frequency field to all READ_FROM_CACHE variants
>       mtd: spinand: Add a ->configure_chip() hook
>       mtd: spinand: winbond: Enable high-speed modes on w25n0xjw
>       mtd: spinand: winbond: Enable high-speed modes on w35n0xjw
>       mtd: spinand: winbond: Add comment about the maximum frequency

Series applied to nand/next after fixing conflicts due to some fixes.

Thanks,
Miquèl