linux-kernel - Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in ufshcd

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Message-ID: <0f3a7ae4-08a1-401a-a41e-cb8db530de36@linaro.org>
Date: Thu, 31 Jul 2025 10:27:51 +0200
From: neil.armstrong@...aro.org
To: Nitin Rawat <quic_nitirawa@...cinc.com>, alim.akhtar@...sung.com,
 avri.altman@....com, bvanassche@....org,
 James.Bottomley@...senPartnership.com, huobean@...il.com, mani@...nel.org,
 martin.petersen@...cle.com, beanhuo@...ron.com, peter.wang@...iatek.com,
 andre.draszik@...aro.org
Cc: linux-arm-msm@...r.kernel.org, linux-scsi@...r.kernel.org,
 linux-kernel@...r.kernel.org, Palash Kambar <quic_pkambar@...cinc.com>
Subject: Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in
 ufshcd_intr

On 29/07/2025 00:57, Nitin Rawat wrote:
> Commit 3c7ac40d7322 ("scsi: ufs: core: Delegate the interrupt service
> routine to a threaded IRQ handler") introduced a regression where
> the UFS interrupt status register (IS) was not cleared in
> ufshcd_intr() when operating in MCQ mode. As a result, the IS register
> remained uncleared.
> 
> This led to a persistent issue during UIC interrupts:
> ufshcd_is_auto_hibern8_error() consistently returned true because the
> UFSHCD_UIC_HIBERN8_MASK bit was set, while the active command was
> neither UIC_CMD_DME_HIBER_ENTER nor UIC_CMD_DME_HIBER_EXIT. This
> caused continuous auto hibern8 enter errors and device failed to boot.
> 
> To fix this, the patch ensures that the interrupt status register is
> properly cleared in the ufshcd_intr() function for both MCQ mode with
> ESI enabled.
> 
> [    4.553226] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: Auto
> Hibern8 Enter failed - status: 0x00000040, upmcrs: 0x00000001
> [    4.553229] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: saved_err
> 0x40 saved_uic_err 0x0
> [    4.553311] host_regs: 00000000: d5c7033f 20e0071f 00000400 00000000
> [    4.553312] host_regs: 00000010: 01000000 00010217 00000c96 00000000
> [    4.553314] host_regs: 00000020: 00000440 00170ef5 00000000 00000000
> [    4.553316] host_regs: 00000030: 0000010f 00000001 00000000 00000000
> [    4.553317] host_regs: 00000040: 00000000 00000000 00000000 00000000
> [    4.553319] host_regs: 00000050: fffdf000 0000000f 00000000 00000000
> [    4.553320] host_regs: 00000060: 00000001 80000000 00000000 00000000
> [    4.553322] host_regs: 00000070: fffde000 0000000f 00000000 00000000
> [    4.553323] host_regs: 00000080: 00000001 00000000 00000000 00000000
> [    4.553325] host_regs: 00000090: 00000002 d0020000 00000000 01930200
> 
> Fixes: 3c7ac40d7322 ("scsi: ufs: core: Delegate the interrupt service routine to a threaded IRQ handler")
> Signed-off-by: Palash Kambar <quic_pkambar@...cinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@...cinc.com>
> 
> ---
>   drivers/ufs/core/ufshcd.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index fd8015ed36a4..5413464d63c8 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -7145,14 +7145,19 @@ static irqreturn_t ufshcd_threaded_intr(int irq, void *__hba)
>   static irqreturn_t ufshcd_intr(int irq, void *__hba)
>   {
>   	struct ufs_hba *hba = __hba;
> +	u32 intr_status, enabled_intr_status;
> 
>   	/* Move interrupt handling to thread when MCQ & ESI are not enabled */
>   	if (!hba->mcq_enabled || !hba->mcq_esi_enabled)
>   		return IRQ_WAKE_THREAD;
> 
> +	intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
> +	enabled_intr_status = intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
> +
> +	ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
> +
>   	/* Directly handle interrupts since MCQ ESI handlers does the hard job */
> -	return ufshcd_sl_intr(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS) &
> -				   ufshcd_readl(hba, REG_INTERRUPT_ENABLE));
> +	return ufshcd_sl_intr(hba, enabled_intr_status);
>   }
> 
>   static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
> --
> 2.48.1
> 
> 

Thanks to [1], I was able to test this change on SM8650-QRD, and it fixed the issue:

Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8650-QRD

Thanks!
Neil

[1] https://lore.kernel.org/all/20250730082229.23475-1-quic_rdwivedi@quicinc.com/