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Message-ID: <d0677ace-0f01-4111-8f00-868d83550b65@acm.org>
Date: Wed, 30 Jul 2025 09:04:57 -0700
From: Bart Van Assche <bvanassche@....org>
To: Peter Wang (王信友) <peter.wang@...iatek.com>,
 "huobean@...il.com" <huobean@...il.com>,
 "avri.altman@....com" <avri.altman@....com>,
 "beanhuo@...ron.com" <beanhuo@...ron.com>,
 "quic_nitirawa@...cinc.com" <quic_nitirawa@...cinc.com>,
 "alim.akhtar@...sung.com" <alim.akhtar@...sung.com>,
 "andre.draszik@...aro.org" <andre.draszik@...aro.org>,
 "martin.petersen@...cle.com" <martin.petersen@...cle.com>,
 "mani@...nel.org" <mani@...nel.org>,
 "James.Bottomley@...senPartnership.com"
 <James.Bottomley@...senPartnership.com>
Cc: "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
 "linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
 "quic_pkambar@...cinc.com" <quic_pkambar@...cinc.com>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in
 ufshcd_intr


On 7/29/25 11:41 PM, Peter Wang (王信友) wrote:
> The threaded ISR was separated out specifically to address
> the issues of the traditional ISR, because a traditional ISR
> must be very fast and short, as it blocks other interrupts.
> But your patch letting the traditional ISR call the threaded
> ISR, doesn’t this bring back the problem where the threaded
> ISR might block other interrupts?
> 
> So, I prefer this patch clear the interrupt status register
> (IS) directly.
Hi Peter,

Thanks for having taken a look but I think that you misunderstood my
patch. My patch does not modify the behavior of the UFS driver on
systems using the legacy single doorbell mode. It only modifies the
behavior on systems supporting MCQ. And on systems that support MCQ, it
restores the behavior from before when commit 3c7ac40d7322 ("scsi: ufs:
core: Delegate the interrupt service routine to a threaded IRQ handler")
got merged.

On MCQ systems, if the completion interrupt is processed by the CPU core
that submitted the I/O, then I/O workloads are self-regulating. The more
time that is spent in the completion interrupt handler, the more the
submitter will be slowed down. This is not the case in legacy single
doorbell mode since when using that mode all completion interrupts are
processed by a single CPU core.

Bart.

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