linux-kernel - Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in ufshcd

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Message-ID: <b005d94288a4c4d29a9361b043354bbc8d85e0e8.camel@mediatek.com>
Date: Wed, 30 Jul 2025 06:41:28 +0000
From: Peter Wang (王信友) <peter.wang@...iatek.com>
To: "huobean@...il.com" <huobean@...il.com>, "avri.altman@....com"
	<avri.altman@....com>, "beanhuo@...ron.com" <beanhuo@...ron.com>,
	"quic_nitirawa@...cinc.com" <quic_nitirawa@...cinc.com>, "bvanassche@....org"
	<bvanassche@....org>, "alim.akhtar@...sung.com" <alim.akhtar@...sung.com>,
	"andre.draszik@...aro.org" <andre.draszik@...aro.org>,
	"martin.petersen@...cle.com" <martin.petersen@...cle.com>, "mani@...nel.org"
	<mani@...nel.org>, "James.Bottomley@...senPartnership.com"
	<James.Bottomley@...senPartnership.com>
CC: "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
	"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
	"quic_pkambar@...cinc.com" <quic_pkambar@...cinc.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in
 ufshcd_intr

On Tue, 2025-07-29 at 09:24 -0700, Bart Van Assche wrote:
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> On 7/29/25 7:37 AM, Nitin Rawat wrote:
> > I reviewed your patch and test it locally—it resolves the issue.
> 
> Thanks!
> 
> > The patch looks good. Since this path handles only UIC, TM, and
> > error
> > conditions with no IO for MCQ, we still check for outstanding_reqs
> > and
> > UTP_TRANSFER_REQ_COMPL for the error case within
> > ufshcd_threaded_intr in
> > the patch. In my opinion, we can skip these additional checks.
> 
> We can only skip the outstanding_reqs check if MCQ is enabled. André
> Draszik is working on a patch that will cause ufshcd_intr() to be
> called
> again for legacy mode so I prefer to keep the outstanding_reqs check.
> 
> Bart.

Hi Bart,

The threaded ISR was separated out specifically to address
the issues of the traditional ISR, because a traditional ISR
must be very fast and short, as it blocks other interrupts.
But your patch letting the traditional ISR call the threaded
ISR, doesn’t this bring back the problem where the threaded
ISR might block other interrupts?

So, I prefer this patch clear the interrupt status register
(IS) directly.

Thanks.
Peter