linux-kernel - Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU

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Message-ID: <0cf62b7f-624c-4751-a126-f0a0b4a6d82d@oss.qualcomm.com>
Date: Thu, 31 Jul 2025 12:12:10 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Neil Armstrong <neil.armstrong@...aro.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8650: Add ACD levels for GPU

On 7/30/25 4:28 PM, Neil Armstrong wrote:
> On 30/07/2025 12:00, Konrad Dybcio wrote:
>> On 7/29/25 4:40 PM, Neil Armstrong wrote:
>>> Update GPU node to include acd level values.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++-
>>>   1 file changed, 13 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> index 495ea9bfd008500dd2c9f46ceca94cf5f972beca..4cd933219ce008bd1c603c87778e210b6332e29c 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> @@ -4127,72 +4127,84 @@ zap-shader {
>>>                 /* Speedbin needs more work on A740+, keep only lower freqs */
>>>               gpu_opp_table: opp-table {
>>> -                compatible = "operating-points-v2";
>>> +                compatible = "operating-points-v2-adreno",
>>> +                         "operating-points-v2";
>>>                     opp-231000000 {
>>>                       opp-hz = /bits/ 64 <231000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>>>                       opp-peak-kBps = <2136718>;
>>> +                    qcom,opp-acd-level = <0xc82f5ffd>;
>>>                   };
>>>                     opp-310000000 {
>>>                       opp-hz = /bits/ 64 <310000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>>>                       opp-peak-kBps = <2136718>;
>>> +                    qcom,opp-acd-level = <0xc82c5ffd>;
>>>                   };
>>
>> https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-devicetree/-/blob/gfx-devicetree-oss.lnx.1.0.r1-rel/gpu/pineapple-v2-gpu-pwrlevels.dtsi?ref_type=heads
>>
>> doesn't set ACD for D1/D2
>>
>>>                     opp-366000000 {
>>>                       opp-hz = /bits/ 64 <366000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>>>                       opp-peak-kBps = <6074218>;
>>> +                    qcom,opp-acd-level = <0xc02e5ffd>;
>>
>> And other values differ too
>>
>> What release did you grab these from?
> 
> A much more recent non-public release with different gpu-pwrlevels for different SKU codes,
> all sets ACDs for D1/D2, and the ACD values are:
> 
> #define ACD_LEVEL_TURBO_L1    0x882a5ffd
> #define ACD_LEVEL_TURBO       0x882a5ffd
> #define ACD_LEVEL_NOM_L1      0x882a5ffd
> #define ACD_LEVEL_NOM         0x882a5ffd
> #define ACD_LEVEL_SVS_L2      0x882a5ffd
> #define ACD_LEVEL_SVS_L1      0x882a5ffd
> #define ACD_LEVEL_SVS_L0      0x882a5ffd
> #define ACD_LEVEL_SVS         0x882c5ffd
> #define ACD_LEVEL_LOW_SVS_L1  0xc02a5ffd
> #define ACD_LEVEL_LOW_SVS     0xc02d5ffd
> #define ACD_LEVEL_LOW_SVS_D0  0xc02e5ffd
> #define ACD_LEVEL_LOW_SVS_D1  0xc82c5ffd
> #define ACD_LEVEL_LOW_SVS_D2  0xc82f5ffd

I found sources confirming this, thanks

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Konrad