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Message-ID: <20250731134759.00000c74@huawei.com>
Date: Thu, 31 Jul 2025 13:47:59 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Yushan Wang <wangyushan12@...wei.com>
CC: <will@...nel.org>, <mark.rutland@....com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<prime.zeng@...ilicon.com>, <fanghao11@...wei.com>, <linuxarm@...wei.com>,
<yangyicong@...ilicon.com>
Subject: Re: [PATCH 8/8] Documentation: hisi-pmu: Add introduction to
HiSilicon V3 PMU
On Tue, 29 Jul 2025 23:38:23 +0800
Yushan Wang <wangyushan12@...wei.com> wrote:
> Some of HiSilicon V3 PMU hardware is divided into parts to fulfill the
> job of monitoring specific parts of a device. Add description on that
> as well as the newly added ext operand for L3C PMU.
>
> Signed-off-by: Yushan Wang <wangyushan12@...wei.com>
There is one fixlet hiding in here that maybe could have been done
as a precursor. I doubt anyone cares though!
Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>
> ---
> Documentation/admin-guide/perf/hisi-pmu.rst | 43 +++++++++++++++++++--
> 1 file changed, 39 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
> index 48992a0b8e94..4c7584fe3c1a 100644
> --- a/Documentation/admin-guide/perf/hisi-pmu.rst
> +++ b/Documentation/admin-guide/perf/hisi-pmu.rst
> @@ -12,15 +12,16 @@ The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
> called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
> two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
>
> -HiSilicon SoC uncore PMU driver
> --------------------------------
> +HiSilicon SoC uncore PMU v1
> +---------------------------
>
> Each device PMU has separate registers for event counting, control and
> interrupt, and the PMU driver shall register perf PMU drivers like L3C,
> HHA and DDRC etc. The available events and configuration options shall
> -be described in the sysfs, see:
> +be described in the sysfs, see::
> +
> +/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
>
> -/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
This is fixing existing stuff so maybe should be a separate patch.
> The "perf list" command shall list the available events from sysfs.
>
> Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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