linux-kernel - Re: [PATCH 8/8] Documentation: hisi-pmu: Add introduction to HiSilicon V3 PMU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <faf78f69-312e-32d1-d0a2-fea908c73218@huawei.com>
Date: Fri, 1 Aug 2025 17:49:56 +0800
From: Yicong Yang <yangyicong@...wei.com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>, Yushan Wang
	<wangyushan12@...wei.com>
CC: <yangyicong@...ilicon.com>, <will@...nel.org>, <mark.rutland@....com>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
	<prime.zeng@...ilicon.com>, <fanghao11@...wei.com>, <linuxarm@...wei.com>
Subject: Re: [PATCH 8/8] Documentation: hisi-pmu: Add introduction to
 HiSilicon V3 PMU

On 2025/7/31 20:47, Jonathan Cameron wrote:
> On Tue, 29 Jul 2025 23:38:23 +0800
> Yushan Wang <wangyushan12@...wei.com> wrote:
> 
>> Some of HiSilicon V3 PMU hardware is divided into parts to fulfill the
>> job of monitoring specific parts of a device.  Add description on that
>> as well as the newly added ext operand for L3C PMU.
>>
>> Signed-off-by: Yushan Wang <wangyushan12@...wei.com>
> There is one fixlet hiding in here that maybe could have been done
> as a precursor.  I doubt anyone cares though!
> 
> Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>
> 
>> ---
>>  Documentation/admin-guide/perf/hisi-pmu.rst | 43 +++++++++++++++++++--
>>  1 file changed, 39 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst
>> index 48992a0b8e94..4c7584fe3c1a 100644
>> --- a/Documentation/admin-guide/perf/hisi-pmu.rst
>> +++ b/Documentation/admin-guide/perf/hisi-pmu.rst
>> @@ -12,15 +12,16 @@ The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
>>  called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
>>  two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
>>  
>> -HiSilicon SoC uncore PMU driver
>> --------------------------------
>> +HiSilicon SoC uncore PMU v1
>> +---------------------------
>>  
>>  Each device PMU has separate registers for event counting, control and
>>  interrupt, and the PMU driver shall register perf PMU drivers like L3C,
>>  HHA and DDRC etc. The available events and configuration options shall
>> -be described in the sysfs, see:
>> +be described in the sysfs, see::
>> +
>> +/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
>>  
>> -/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
> 
> This is fixing existing stuff so maybe should be a separate patch.
> 

maybe it's just a format change (paragraph text to block text) so not worth backporting.
that's why I didn't see any warnings when compile.

thanks.