linux-kernel - Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in ufshcd

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <2e96a5843fe393537c3325dc2d5af5306686330c.camel@mediatek.com>
Date: Fri, 1 Aug 2025 07:31:40 +0000
From: Peter Wang (王信友) <peter.wang@...iatek.com>
To: "huobean@...il.com" <huobean@...il.com>, "avri.altman@....com"
	<avri.altman@....com>, "beanhuo@...ron.com" <beanhuo@...ron.com>,
	"quic_nitirawa@...cinc.com" <quic_nitirawa@...cinc.com>, "bvanassche@....org"
	<bvanassche@....org>, "alim.akhtar@...sung.com" <alim.akhtar@...sung.com>,
	"andre.draszik@...aro.org" <andre.draszik@...aro.org>,
	"martin.petersen@...cle.com" <martin.petersen@...cle.com>, "mani@...nel.org"
	<mani@...nel.org>, "James.Bottomley@...senPartnership.com"
	<James.Bottomley@...senPartnership.com>
CC: "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
	"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
	"quic_pkambar@...cinc.com" <quic_pkambar@...cinc.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V1] ufs: core: Fix interrupt handling for MCQ Mode in
 ufshcd_intr

On Tue, 2025-07-29 at 04:27 +0530, Nitin Rawat wrote:
> Commit 3c7ac40d7322 ("scsi: ufs: core: Delegate the interrupt service
> routine to a threaded IRQ handler") introduced a regression where
> the UFS interrupt status register (IS) was not cleared in
> ufshcd_intr() when operating in MCQ mode. As a result, the IS
> register
> remained uncleared.
> 
> This led to a persistent issue during UIC interrupts:
> ufshcd_is_auto_hibern8_error() consistently returned true because the
> UFSHCD_UIC_HIBERN8_MASK bit was set, while the active command was
> neither UIC_CMD_DME_HIBER_ENTER nor UIC_CMD_DME_HIBER_EXIT. This
> caused continuous auto hibern8 enter errors and device failed to
> boot.
> 
> To fix this, the patch ensures that the interrupt status register is
> properly cleared in the ufshcd_intr() function for both MCQ mode with
> ESI enabled.
> 
> [    4.553226] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors: Auto
> Hibern8 Enter failed - status: 0x00000040, upmcrs: 0x00000001
> [    4.553229] ufshcd-qcom 1d84000.ufs: ufshcd_check_errors:
> saved_err
> 0x40 saved_uic_err 0x0
> [    4.553311] host_regs: 00000000: d5c7033f 20e0071f 00000400
> 00000000
> [    4.553312] host_regs: 00000010: 01000000 00010217 00000c96
> 00000000
> [    4.553314] host_regs: 00000020: 00000440 00170ef5 00000000
> 00000000
> [    4.553316] host_regs: 00000030: 0000010f 00000001 00000000
> 00000000
> [    4.553317] host_regs: 00000040: 00000000 00000000 00000000
> 00000000
> [    4.553319] host_regs: 00000050: fffdf000 0000000f 00000000
> 00000000
> [    4.553320] host_regs: 00000060: 00000001 80000000 00000000
> 00000000
> [    4.553322] host_regs: 00000070: fffde000 0000000f 00000000
> 00000000
> [    4.553323] host_regs: 00000080: 00000001 00000000 00000000
> 00000000
> [    4.553325] host_regs: 00000090: 00000002 d0020000 00000000
> 01930200
> 
> Fixes: 3c7ac40d7322 ("scsi: ufs: core: Delegate the interrupt service
> routine to a threaded IRQ handler")
> Signed-off-by: Palash Kambar <quic_pkambar@...cinc.com>
> Signed-off-by: Nitin Rawat <quic_nitirawa@...cinc.com>
> 

Reviewed-by: Peter Wang <peter.wang@...iatek.com>