[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <46590c06-a9e5-4469-873a-ec312f70cc9a@kernel.org>
Date: Sun, 3 Aug 2025 10:15:47 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Laura Nao <laura.nao@...labora.com>, mturquette@...libre.com,
sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
matthias.bgg@...il.com, angelogioacchino.delregno@...labora.com,
p.zabel@...gutronix.de, richardcochran@...il.com
Cc: guangjie.song@...iatek.com, wenst@...omium.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
kernel@...labora.com, NĂcolas F . R . A . Prado
<nfraprado@...labora.com>
Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196
clock controllers
On 30/07/2025 12:56, Laura Nao wrote:
> +
> + mediatek,hardware-voter:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
> + MCU manages clock and power domain control across the AP and other
> + remote processors. By aggregating their votes, it ensures clocks are
> + safely enabled/disabled and power domains are active before register
> + access.
No improvements, I already commented on this.
I also said:
"I already commented on this, so don't send v3 with the same."
NAK
Best regards,
Krzysztof
Powered by blists - more mailing lists