linux-kernel - Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers

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Message-ID: <fbe7b083-bc3f-4156-8056-e45c9adcb607@kernel.org>
Date: Sun, 3 Aug 2025 10:17:21 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Rob Herring <robh@...nel.org>, Laura Nao <laura.nao@...labora.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, matthias.bgg@...il.com,
 angelogioacchino.delregno@...labora.com, p.zabel@...gutronix.de,
 richardcochran@...il.com, guangjie.song@...iatek.com, wenst@...omium.org,
 linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
 kernel@...labora.com, Nícolas F . R . A . Prado
 <nfraprado@...labora.com>
Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196
 clock controllers

On 01/08/2025 15:57, Rob Herring wrote:
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  '#reset-cells':
>> +    const: 1
>> +    description:
>> +      Reset lines for PEXTP0/1 and UFS blocks.
>> +
>> +  mediatek,hardware-voter:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
>> +      MCU manages clock and power domain control across the AP and other
>> +      remote processors. By aggregating their votes, it ensures clocks are
>> +      safely enabled/disabled and power domains are active before register
>> +      access.
> 
> I thought this was going away based on v2 discussion?

Yes, I asked to drop it and do not include it in v3. There was also
discussion clarifying review.

I am really surprised that review meant nothing and code is still the same.

Best regards,
Krzysztof