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Message-Id: <20250804083540.19099-1-laura.nao@collabora.com>
Date: Mon, 4 Aug 2025 10:35:40 +0200
From: Laura Nao <laura.nao@...labora.com>
To: krzk@...nel.org
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Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers
Hi,
On 8/3/25 10:17, Krzysztof Kozlowski wrote:
> On 01/08/2025 15:57, Rob Herring wrote:
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + '#clock-cells':
>>> + const: 1
>>> +
>>> + '#reset-cells':
>>> + const: 1
>>> + description:
>>> + Reset lines for PEXTP0/1 and UFS blocks.
>>> +
>>> + mediatek,hardware-voter:
>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>> + description:
>>> + On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
>>> + MCU manages clock and power domain control across the AP and other
>>> + remote processors. By aggregating their votes, it ensures clocks are
>>> + safely enabled/disabled and power domains are active before register
>>> + access.
>>
>> I thought this was going away based on v2 discussion?
>
> Yes, I asked to drop it and do not include it in v3. There was also
> discussion clarifying review.
>
> I am really surprised that review meant nothing and code is still the same.
>
This has been re-submitted as-is, following the outcome of the discussion
here: https://lore.kernel.org/all/242bf682-cf8f-4469-8a0b-9ec982095f04@collabora.com/
We haven't found a viable alternative to the current approach so far, and
the thread outlines why other options don’t apply. I'm happy to continue
the discussion there if anyone has further suggestions or ideas on how
to address this.
Thanks,
Laura
> Best regards,
> Krzysztof
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