lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <b5775270-5306-4eb7-9fe5-44b087b20c40@kernel.org>
Date: Mon, 4 Aug 2025 09:26:55 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Andrei Stefanescu <andrei.stefanescu@....nxp.com>,
 Arnd Bergmann <arnd@...db.de>, Linus Walleij <linus.walleij@...aro.org>,
 Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>,
 krzk+dt@...nel.org, Conor Dooley <conor+dt@...nel.org>,
 Chester Lin <chester62515@...il.com>, Matthias Brugger <mbrugger@...e.com>,
 Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>,
 Larisa Grigore <larisa.grigore@....com>, Lee Jones <lee@...nel.org>,
 Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
 Fabio Estevam <festevam@...il.com>, aisheng.dong@....com,
 Jacky Bai <ping.bai@....com>, Greg Kroah-Hartman
 <gregkh@...uxfoundation.org>, "Rafael J . Wysocki" <rafael@...nel.org>,
 Srinivas Kandagatla <srini@...nel.org>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, NXP S32 Linux Team <s32@....com>,
 Christophe Lizzi <clizzi@...hat.com>, Alberto Ruiz <aruizrui@...hat.com>,
 Enric Balletbo <eballetb@...hat.com>, echanude@...hat.com,
 Pengutronix Kernel Team <kernel@...gutronix.de>, imx@...ts.linux.dev,
 Vincent Guittot <vincent.guittot@...aro.org>
Subject: Re: [PATCH v7 10/12] nvmem: s32g2_siul2: add NVMEM driver for SoC
 information

On 04/08/2025 09:12, Andrei Stefanescu wrote:
> Hi Krzysztof,
> 
> Thank you for the quick response!
> On 02/08/2025 11:32, Krzysztof Kozlowski wrote:
>> On 02/08/2025 10:28, Krzysztof Kozlowski wrote:
>>> On 01/08/2025 16:36, Andrei Stefanescu wrote:
>>>> Apart from the proposed NVMEM driver, there is also an option of exporting
>>>> a syscon regmap for the registers which provide information about the SoC.
>>>>
>>>> I have seen that typically NVMEM drivers export information read from fuses
>>>> but I think having a NVMEM driver is nicer way to access the information
>>>> instead of using a syscon regmap and manually extracting the needed bits. 
>>>
>>>
>>> nvmem is not a syscon. Mixing these two means device is something
>>> completely else.
> 
> Yes, I don't want to mix them. The driver will either be a NVMEM driver or
> a syscon. These registers are read-only. I suggested NVMEM because it's a

We do not talk about drivers here, but hardware.

> an abstraction layer which makes it easier for drivers which want to use
> that information without knowing where to actually read it i.e. reg address,
> bit mask.

Sorry, but no. You design it for drivers, that's not the way. Describe
properly the hardware.


Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ