linux-kernel - RE: [PATCH v12 3/3] clk: aspeed: add AST2700 clock driver

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Message-ID:
 <OS8PR06MB75412CE3A7A3DB8E6D6A1A55F22DA@OS8PR06MB7541.apcprd06.prod.outlook.com>
Date: Wed, 6 Aug 2025 05:29:01 +0000
From: Ryan Chen <ryan_chen@...eedtech.com>
To: Andrew Lunn <andrew@...n.ch>, Mo Elbadry <elbadrym@...gle.com>, Jacky Chou
	<jacky_chou@...eedtech.com>
CC: Michael Turquette <mturquette@...libre.com>, Stephen Boyd
	<sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, Joel Stanley
	<joel@....id.au>, Andrew Jeffery <andrew@...econstruct.com.au>, Rob Herring
	<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
	<conor+dt@...nel.org>, "linux-clk@...r.kernel.org"
	<linux-clk@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-aspeed@...ts.ozlabs.org"
	<linux-aspeed@...ts.ozlabs.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, Rom Lemarchand <romlem@...gle.com>, William
 Kennington <wak@...gle.com>, Yuxiao Zhang <yuxiaozhang@...gle.com>,
	"wthai@...dia.com" <wthai@...dia.com>, "leohu@...dia.com" <leohu@...dia.com>,
	"dkodihalli@...dia.com" <dkodihalli@...dia.com>, "spuranik@...dia.com"
	<spuranik@...dia.com>
Subject: RE: [PATCH v12 3/3] clk: aspeed: add AST2700 clock driver

> Subject: Re: [PATCH v12 3/3] clk: aspeed: add AST2700 clock driver
> 
> > > > +static const struct clk_div_table ast2700_rgmii_div_table[] = {
> > > > +     { 0x0, 4 },
> > > > +     { 0x1, 4 },
> > > > +     { 0x2, 6 },
> > > > +     { 0x3, 8 },
> > > > +     { 0x4, 10 },
> > > > +     { 0x5, 12 },
> > > > +     { 0x6, 14 },
> > > > +     { 0x7, 16 },
> > > > +     { 0 }
> > > > +};
> 
> > > > +     DIVIDER_CLK(SCU1_CLK_RGMII, "rgmii", soc1_hpll,
> > > > +                 SCU1_CLK_SEL1, 25, 3, ast2700_rgmii_div_table),
> 
> 
> Historically, aspeed has got RGMII delays wrong. Could you confirm this has
> nothing to do with the 2ns delay needed by RGMII.

It is nothing to do with this delay cell.
> 
> What exactly is this clock used for? RGMII needs 2.5MHz, 25MHz and 125MHz,
> which none of these dividers seems to provide.

It is RGMII clk source for MAC controller.
The clock tree is hpll-> div -> mac rgmii, and MAC controller will generate 2.5, 25,
125Mhz depend on mode. 

> 
> 	Andrew