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Message-ID: <385d9185-e187-48c2-9854-10cdd98d2f1b@ti.com>
Date: Wed, 6 Aug 2025 11:25:19 +0530
From: devarsh <devarsht@...com>
To: Harikrishna Shenoy <h-shenoy@...com>, <vkoul@...nel.org>,
<kishon@...nel.org>, <u.kleine-koenig@...libre.com>,
<linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<u-kumar1@...com>, <s-jain1@...com>
Subject: Re: [PATCH v2] drivers: phy: cadence: cdns-dphy: Enable lower
resolutions in dphy
On 06/08/25 10:56, Harikrishna Shenoy wrote:
> Enable support for hs_clk_rate between 80-160 Mbps cdns dphy
Enable support for data lane rates between 80-160 Mbps
> as mentioned in TRM [0] by setting the pll_opdiv field to 16.
> This change enables lower resolutions like 640x480 at 60Hz.
>
> [0]: https://www.ti.com/lit/zip/spruil1
> (Table 12-552. DPHY_TX_PLL_CTRL Register Field Descriptions)
>
> Reviewed-by: Udit Kumar <u-kumar1@...com>
> Signed-off-by: Harikrishna Shenoy <h-shenoy@...com>
With suggested change,
Reviewed-by: Devarsh Thakkar <devarsht@...com>
Regards
Devarsh
> ---
> Changes in v2:
> - Updated commit message and title.
> - Added Reviewed-by tag.
> - Link to v1: https://lore.kernel.org/all/1ebb82ea-4b6c-4496-b7c0-17d4168d8ddf@ti.com/
>
> Test log: https://gist.github.com/h-shenoy/3975156baf403a0ff8dbcce5b49b2b89
>
> drivers/phy/cadence/cdns-dphy.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
> index ed87a3970f83..9abed2ece9b0 100644
> --- a/drivers/phy/cadence/cdns-dphy.c
> +++ b/drivers/phy/cadence/cdns-dphy.c
> @@ -139,7 +139,7 @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
>
> dlane_bps = opts->hs_clk_rate;
>
> - if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
> + if (dlane_bps > 2500000000UL || dlane_bps < 80000000UL)
> return -EINVAL;
> else if (dlane_bps >= 1250000000)
> cfg->pll_opdiv = 1;
> @@ -149,6 +149,8 @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
> cfg->pll_opdiv = 4;
> else if (dlane_bps >= 160000000)
> cfg->pll_opdiv = 8;
> + else if (dlane_bps >= 80000000)
> + cfg->pll_opdiv = 16;
>
> cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
> cfg->pll_ipdiv,
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