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Message-ID: <CAMuHMdVhxxJprKSr3-QmO-8+ue+guqErW5e1tj3yEHRMZhdeiQ@mail.gmail.com>
Date: Wed, 6 Aug 2025 16:47:50 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, Bartosz Golaszewski <brgl@...ev.pl>, linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Thierry Bultel <thierry.bultel.yh@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v4 2/3] pinctrl: renesas: Add support for RZ/T2H
Hi Prabhakar,
On Fri, 1 Aug 2025 at 17:46, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
>
> Add the pinctrl and gpio driver for RZ/T2H
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v3->v4:
> - No changes
>
> v2->v3:
> - Fixed Kconfig dependency.
> - Added dependency for 64bit to avoid build errors on 32bit systems.
> - Included bitfield.h
Thanks for the update!
Seems like several of my review comments on v1 were missed.
> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> +#define PM_MASK GENMASK(1, 0)
> +#define PM_PIN_MASK(pin) (PM_MASK << ((pin) * 2))
Please move PM_INPUT and PM_OUTPUT here, and insert a blank line
between the PM_* and PFC_* definitions.
> +#define PFC_MASK GENMASK_ULL(5, 0)
> +#define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8))
> +
> +#define PM_INPUT 0x01
BIT(0)
> +#define PM_OUTPUT 0x02
BIT(1)
> +struct rzt2h_pinctrl_data {
> + const char * const *port_pins;
Do you need this? It always points rzt2h_gpio_names[].
> + unsigned int n_port_pins;
> + const u8 *port_pin_configs;
> + unsigned int n_ports;
> +};
> +
> +struct rzt2h_pinctrl {
> + struct pinctrl_dev *pctl;
> + struct pinctrl_desc desc;
> + struct pinctrl_pin_desc *pins;
> + const struct rzt2h_pinctrl_data *data;
> + void __iomem *base0, *base1;
> + struct device *dev;
> + struct gpio_chip gpio_chip;
> + struct pinctrl_gpio_range gpio_range;
> + spinlock_t lock;
> + struct mutex mutex;
Please add comments to these two locks, to clarify what they are
protecting against.
> + bool safety_port_enabled;
> +};
> +
> +#define RZT2H_PINCTRL_REG_ACCESS(size, type) \
> +static inline void rzt2h_pinctrl_write##size(struct rzt2h_pinctrl *pctrl, u8 port, \
> + type val, u16 offset) \
unsigned int offset?
> +{ \
> + if (port > RZT2H_MAX_SAFETY_PORTS) \
> + write##size(val, pctrl->base0 + offset); \
> + else \
> + write##size(val, pctrl->base1 + offset); \
> +} \
> +\
> +static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port, u16 offset) \
Likewise
> +{ \
> + if (port > RZT2H_MAX_SAFETY_PORTS) \
> + return read##size(pctrl->base0 + offset); \
> + else \
> + return read##size(pctrl->base1 + offset); \
> +}
> +static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
> +{
> + u8 port = RZT2H_PIN_ID_TO_PORT(offset);
> + u8 pin = RZT2H_PIN_ID_TO_PIN(offset);
> + u8 pincfg;
> +
> + if (offset >= pctrl->data->n_port_pins || port >= pctrl->data->n_ports)
> + return -EINVAL;
> +
> + if (!pctrl->safety_port_enabled && port <= RZT2H_MAX_SAFETY_PORTS)
> + return -EINVAL;
> +
> + pincfg = pctrl->data->port_pin_configs[port];
> + return (pincfg & (1 << pin)) ? 0 : -EINVAL;
BIT(pin)
> +}
> +
> +static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev,
> + unsigned int func_selector,
> + unsigned int group_selector)
> +{
> + struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> + struct function_desc *func;
> + struct group_desc *group;
> + const unsigned int *pins;
> + unsigned int i;
> + u8 *psel_val;
> + int ret;
> +
> + func = pinmux_generic_get_function(pctldev, func_selector);
> + if (!func)
> + return -EINVAL;
> + group = pinctrl_generic_get_group(pctldev, group_selector);
> + if (!group)
> + return -EINVAL;
> +
> + psel_val = func->data;
> + pins = group->grp.pins;
> +
> + for (i = 0; i < group->grp.npins; i++) {
> + dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
Please use consistent spacing around colons.
> + RZT2H_PIN_ID_TO_PORT(pins[i]), RZT2H_PIN_ID_TO_PIN(pins[i]),
> + psel_val[i]);
> + ret = rzt2h_validate_pin(pctrl, pins[i]);
> + if (ret)
> + return ret;
Please insert a blank line.
> + rzt2h_pinctrl_set_pfc_mode(pctrl, RZT2H_PIN_ID_TO_PORT(pins[i]),
> + RZT2H_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
> + }
> +
> + return 0;
> +};
> +static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
> + u8 port = RZT2H_PIN_ID_TO_PORT(offset);
> + u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
> + int ret;
> +
> + ret = rzt2h_validate_pin(pctrl, offset);
> + if (ret)
> + return ret;
> +
> + if (!(rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit))) {
Invert the logic and return early, to reduce indentation?
> + u16 reg;
> +
> + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
> + reg = (reg >> (bit * 2)) & PM_MASK;
> + if (reg == PM_OUTPUT)
The hardware supports enabling both input and output, so I think you
better check for "reg & PM_OUTPUT".
> + return GPIO_LINE_DIRECTION_OUT;
> + if (reg == PM_INPUT)
> + return GPIO_LINE_DIRECTION_IN;
> + }
> +
> + return -EINVAL;
> +}
> +static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
> + u8 port = RZT2H_PIN_ID_TO_PORT(offset);
> + u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
> + u16 reg;
> +
> + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
> + reg = (reg >> (bit * 2)) & PM_MASK;
> +
> + if (reg == PM_INPUT)
"if (reg & PM_INPUT)", to handle both PM_INPUT and PM_OUTPUT set?
> + return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit));
> + if (reg == PM_OUTPUT)
> + return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit));
> + return -EINVAL;
> +}
> +static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl)
> +{
> + struct pinctrl_desc *desc = &pctrl->desc;
> + struct device *dev = pctrl->dev;
> + struct pinctrl_pin_desc *pins;
> + unsigned int i, j;
> + u8 *pin_data;
> + int ret;
> +
> + desc->name = DRV_NAME;
> + desc->npins = pctrl->data->n_port_pins;
> + desc->pctlops = &rzt2h_pinctrl_pctlops;
> + desc->pmxops = &rzt2h_pinctrl_pmxops;
> + desc->owner = THIS_MODULE;
> +
> + pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);
> + if (!pins)
> + return -ENOMEM;
> +
> + pin_data = devm_kcalloc(dev, desc->npins,
> + sizeof(*pin_data), GFP_KERNEL);
Fits on a single line.
> + if (!pin_data)
> + return -ENOMEM;
> +
> + pctrl->pins = pins;
> + desc->pins = pins;
> +
> + for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
> + pins[i].number = i;
> + pins[i].name = pctrl->data->port_pins[i];
> + if (i && !(i % RZT2H_PINS_PER_PORT))
> + j++;
> + pin_data[i] = pctrl->data->port_pin_configs[j];
> + pins[i].drv_data = &pin_data[i];
Where is this used?
> + }
> +
> + ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl);
> + if (ret)
> + return dev_err_probe(dev, ret, "pinctrl registration failed\n");
> +
> + ret = pinctrl_enable(pctrl->pctl);
> + if (ret)
> + return dev_err_probe(dev, ret, "pinctrl enable failed\n");
> +
> + return rzt2h_gpio_register(pctrl);
> +}
> +
> +static int rzt2h_pinctrl_cfg_regions(struct platform_device *pdev,
> + struct rzt2h_pinctrl *pctrl)
> +{
> + pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr");
> + if (IS_ERR(pctrl->base0))
> + return PTR_ERR(pctrl->base0);
> +
> + pctrl->base1 = devm_platform_ioremap_resource_byname(pdev, "srs");
When the optional "srs" region is missing, it is ignored by the
code below, but __devm_ioremap_resource() will still have printed
an error message. So you either have to open-code this using
platform_get_resource_byname() and devm_ioremap_resource() here, or
create a static devm_platform_ioremap_resource_byname_optional()
helper that does the same, or go for a public helper directly.
> + if (IS_ERR(pctrl->base1)) {
> + if (PTR_ERR(pctrl->base1) != -EINVAL)
> + return PTR_ERR(pctrl->base1);
> + } else {
> + u8 port;
> +
> + pctrl->safety_port_enabled = true;
> +
> + /* Configure to select safety region 0x812c0xxx */
> + for (port = 0; port <= RZT2H_MAX_SAFETY_PORTS; port++)
> + writeb(0x0, pctrl->base1 + RSELP(port));
> + }
> +
> + return 0;
> +}
> +static const u8 r9a09g077_gpio_configs[] = {
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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