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Message-ID: <CAMuHMdVv=AT3G8njFfGU8=gwwGX6G55TdTpspdwX=HBWdsGGNg@mail.gmail.com>
Date: Wed, 6 Aug 2025 16:49:47 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, Bartosz Golaszewski <brgl@...ev.pl>, linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v4 3/3] pinctrl: renesas: rzt2h: Add support for RZ/N2H SoC
Hi Prabhakar,
On Fri, 1 Aug 2025 at 17:46, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> The RZ/N2H (R9A09G087) SoC from Renesas shares a similar pin controller
> architecture with the RZ/T2H (R9A09G077) SoC, differing primarily in the
> number of supported pins-576 on RZ/N2H versus 729 on RZ/T2H.
>
> Add the necessary pin configuration data and compatible string to enable
> support for the RZ/N2H SoC in the RZ/T2H pinctrl driver.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/Kconfig
> +++ b/drivers/pinctrl/renesas/Kconfig
> @@ -304,7 +305,7 @@ config PINCTRL_RZN1
> This selects pinctrl driver for Renesas RZ/N1 devices.
>
> config PINCTRL_RZT2H
> - bool "pin control support for RZ/T2H" if COMPILE_TEST
> + bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST
Do you plan to update this for each new SoC?
> depends on 64BIT && OF
> select GPIOLIB
> select GENERIC_PINCTRL_GROUPS
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> index 877f6d00830f..55c64d74cb54 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> @@ -764,6 +764,12 @@ static const u8 r9a09g077_gpio_configs[] = {
> 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
> };
>
> +static const u8 r9a09g087_gpio_configs[] = {
> + 0x1f, 0xff, 0xff, 0x1f, 0, 0xfe, 0xff, 0, 0x7e, 0xf0, 0xff, 0x1,
> + 0xff, 0xff, 0xff, 0, 0xe0, 0xff, 0xff, 0, 0xff, 0xff, 0xff, 0x1,
> + 0xe0, 0xff, 0xff, 0x7f, 0, 0xfe, 0xff, 0x7f, 0, 0xfc, 0x7f,
Please always use 0xXX for consistent formatting.
> +};
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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