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Message-ID: <CA+V-a8tkPVoe1Q0cSdzjTMKyrdkVsJnUzXBRvb0DO1s-h5zrxw@mail.gmail.com>
Date: Wed, 6 Aug 2025 16:21:02 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Linus Walleij <linus.walleij@...aro.org>, linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
John Madieu <john.madieu.xa@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 5/7] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}
Hi Geert,
Thank you for the review.
On Wed, Aug 6, 2025 at 1:57 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing
> > rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a
> > pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit
> > positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR
> > locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded
> > PFC_OEN define and obsolete per-SoC OEN helpers.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>
> > @@ -270,6 +270,7 @@ struct rzg2l_hwcfg {
> > u8 func_base;
> > u8 oen_max_pin;
> > u8 oen_max_port;
> > + bool oen_pwpr_lock;
>
> While u8 and bool do have the same size, please keep the bools grouped
> ogether.
>
Ok, I will move it above `func_base` member.
Cheers,
Prabhakar
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