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Message-ID: <CAAhV-H5XQ9+dL+QE50aO3XNZ4ic9QqA5frMi8y+eMb83Dv0Gyw@mail.gmail.com> Date: Thu, 7 Aug 2025 12:44:27 +0800 From: Huacai Chen <chenhuacai@...nel.org> To: Yao Zi <ziyao@...root.org> Cc: Yinbo Zhu <zhuyinbo@...ngson.cn>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, WANG Xuerui <kernel@...0n.name>, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, loongarch@...ts.linux.dev, Mingcong Bai <jeffbai@...c.io>, Kexy Biscuit <kexybiscuit@...c.io> Subject: Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible On Wed, Aug 6, 2025 at 8:30 PM Yao Zi <ziyao@...root.org> wrote: > > On Wed, Aug 06, 2025 at 04:36:50PM +0800, Huacai Chen wrote: > > On Tue, Aug 5, 2025 at 11:03 PM Yao Zi <ziyao@...root.org> wrote: > > > > > > Document the clock controller shipped in Loongson 2K0300 SoC, which > > > generates various clock signals for SoC peripherals. > > > > > > Differing from previous generations of SoCs, 2K0300 requires a 120MHz > > > external clock input, and a separate dt-binding header is used for > > > cleanness. > > > > > > Signed-off-by: Yao Zi <ziyao@...root.org> > > > --- > > > .../bindings/clock/loongson,ls2k-clk.yaml | 21 ++++++-- > > > MAINTAINERS | 1 + > > > .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++ > > > 3 files changed, 72 insertions(+), 4 deletions(-) > > > create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h > > > > > ... > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > index 4912b8a83bbb..7960e65d7dfc 100644 > > > --- a/MAINTAINERS > > > +++ b/MAINTAINERS > > > @@ -14365,6 +14365,7 @@ S: Maintained > > > F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml > > > F: drivers/clk/clk-loongson2.c > > > F: include/dt-bindings/clock/loongson,ls2k-clk.h > > > +F: include/dt-bindings/clock/loongson,ls2k0300-clk.h > > I think ls2k0300-clk.h can be merged into ls2k-clk.h > > Honestly I think a separate header makes the purpose more clear, and > follows the convention that name of binding header matches the > compatible, but I'm willing to change if you really consider merging > them together is better and dt-binding maintainer agrees on this. I think merging is better, because: 1, loongson,ls2k-clk.h has already contains ls2k500, ls2k1000, ls2k2000, so ls2k300 is not special. 2, ls2k500, ls2k1000, ls2k2000 and ls2k300 use the same driver (drivers/clk/clk-loongson2.c), it is not necessary to include two headers. And moreover, existing code uses NODE_PLL/DDR_PLL naming, ls2k300 uses PLL_NODE/PLL_DDR is not so good. Huacai > > > Huacai > > Thanks, > Yao Zi > > > > > > > LOONGSON SPI DRIVER > > > M: Yinbo Zhu <zhuyinbo@...ngson.cn> > > > diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h > > > new file mode 100644 > > > index 000000000000..5e8f7b2f33f2 > > > --- /dev/null > > > +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h > > > @@ -0,0 +1,54 @@ > > > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ > > > +/* > > > + * Copyright (C) 2025 Yao Zi <ziyao@...root.org> > > > + */ > > > +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > > > +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > > > + > > > +/* Derivied from REFCLK */ > > > +#define LS2K0300_CLK_STABLE 0 > > > +#define LS2K0300_PLL_NODE 1 > > > +#define LS2K0300_PLL_DDR 2 > > > +#define LS2K0300_PLL_PIX 3 > > > +#define LS2K0300_CLK_THSENS 4 > > > + > > > +/* Derived from PLL_NODE */ > > > +#define LS2K0300_CLK_NODE_DIV 5 > > > +#define LS2K0300_CLK_NODE_PLL_GATE 6 > > > +#define LS2K0300_CLK_NODE_SCALE 7 > > > +#define LS2K0300_CLK_NODE_GATE 8 > > > +#define LS2K0300_CLK_GMAC_DIV 9 > > > +#define LS2K0300_CLK_GMAC_GATE 10 > > > +#define LS2K0300_CLK_I2S_DIV 11 > > > +#define LS2K0300_CLK_I2S_SCALE 12 > > > +#define LS2K0300_CLK_I2S_GATE 13 > > > + > > > +/* Derived from PLL_DDR */ > > > +#define LS2K0300_CLK_DDR_DIV 14 > > > +#define LS2K0300_CLK_DDR_GATE 15 > > > +#define LS2K0300_CLK_NET_DIV 16 > > > +#define LS2K0300_CLK_NET_GATE 17 > > > +#define LS2K0300_CLK_DEV_DIV 18 > > > +#define LS2K0300_CLK_DEV_GATE 19 > > > + > > > +/* Derived from PLL_PIX */ > > > +#define LS2K0300_CLK_PIX_DIV 20 > > > +#define LS2K0300_CLK_PIX_PLL_GATE 21 > > > +#define LS2K0300_CLK_PIX_SCALE 22 > > > +#define LS2K0300_CLK_PIX_GATE 23 > > > +#define LS2K0300_CLK_GMACBP_DIV 24 > > > +#define LS2K0300_CLK_GMACBP_GATE 25 > > > + > > > +/* Derived from CLK_DEV */ > > > +#define LS2K0300_CLK_USB_SCALE 26 > > > +#define LS2K0300_CLK_USB_GATE 27 > > > +#define LS2K0300_CLK_APB_SCALE 28 > > > +#define LS2K0300_CLK_APB_GATE 29 > > > +#define LS2K0300_CLK_BOOT_SCALE 30 > > > +#define LS2K0300_CLK_BOOT_GATE 31 > > > +#define LS2K0300_CLK_SDIO_SCALE 32 > > > +#define LS2K0300_CLK_SDIO_GATE 33 > > > + > > > +#define LS2K0300_CLK_GMAC_IN 34 > > > + > > > +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > > > -- > > > 2.50.1 > > > > > >
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