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Message-ID: <20250807000207.GE184255@nvidia.com>
Date: Wed, 6 Aug 2025 21:02:07 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Alex Williamson <alex.williamson@...hat.com>
Cc: Leon Romanovsky <leon@...nel.org>, Leon Romanovsky <leonro@...dia.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Christian König <christian.koenig@....com>,
Christoph Hellwig <hch@....de>, dri-devel@...ts.freedesktop.org,
iommu@...ts.linux.dev, Jens Axboe <axboe@...nel.dk>,
Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
linaro-mm-sig@...ts.linaro.org, linux-block@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-media@...r.kernel.org,
linux-mm@...ck.org, linux-pci@...r.kernel.org,
Logan Gunthorpe <logang@...tatee.com>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Robin Murphy <robin.murphy@....com>,
Sumit Semwal <sumit.semwal@...aro.org>,
Vivek Kasireddy <vivek.kasireddy@...el.com>,
Will Deacon <will@...nel.org>
Subject: Re: [PATCH v1 04/10] PCI/P2PDMA: Refactor to separate core P2P
functionality from memory allocation
On Wed, Aug 06, 2025 at 03:42:14PM -0600, Alex Williamson wrote:
> > + p2p->mem.owner = &pdev->dev;
> > + /* On all p2p platforms bus_offset is the same for all BARs */
> > + p2p->mem.bus_offset =
> > + pci_bus_address(pdev, 0) - pci_resource_start(pdev, 0);
>
> But not all devices implement BAR0, nor is BAR0 necessarily in the
> memory space, wouldn't this calculation be wrong if BAR0 were
> unimplemented or an IO BAR?
I think you are correct about this.
> Even within memory BARs I can imagine different translations for 32
> vs 64 bit, prefetch vs non-prefetch, but per the comment I guess
> we're excluding those. Thanks,
Humm, I had thought it was consistent for the device, but I guess not:
resource_list_for_each_entry(window, &bridge->windows) {
if (resource_contains(window->res, res)) {
offset = window->offset;
Seems like each window can have its own offset.
So the p2p should be made per-bar, and hold the bar index from the
constructor..
Jason
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