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Message-ID: <7bptwqmqimkuixgo3zvwfafktx7sj6a5xzfcedip6vuudhwmqt@ey7cs7x2ucxr>
Date: Sat, 9 Aug 2025 10:49:57 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Konrad Dybcio <konradybcio@...nel.org>, Nikita Travkin <nikita@...n.ru>
Cc: cros-qcom-dts-watchers@...omium.org,
Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent
data paths
On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>
> Define ports {} for the DWC controller & the QMPPHY and connect them
> together for the SS lanes.
>
> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
If I remember correctly, on SC7180 the DP is still routed through USB+DP
combo PHY rather than having a separate output. I'd let Nikita to
comment though.
For the patch:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> Take the creative liberty to add a newline before its ports' subnodes
> though.
>
> [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/
>
> Suggested-by: Rob Herring (Arm) <robh@...nel.org>
> Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
--
With best wishes
Dmitry
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