linux-kernel - Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

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Message-ID: <4478d71458f7ae1501de6cc1a65e98e3@trvn.ru>
Date: Sat, 09 Aug 2025 14:43:47 +0500
From: Nikita Travkin <nikita@...n.ru>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Konrad Dybcio <konradybcio@...nel.org>,
 cros-qcom-dts-watchers@...omium.org, Bjorn Andersson <andersson@...nel.org>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Marijn Suijten
 <marijn.suijten@...ainline.org>, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Konrad Dybcio
 <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent
 data paths

Dmitry Baryshkov писал(а) 09.08.2025 12:49:
> On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>> 
>> Define ports {} for the DWC controller & the QMPPHY and connect them
>> together for the SS lanes.
>> 
>> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
>> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
> 
> If I remember correctly, on SC7180 the DP is still routed through USB+DP
> combo PHY rather than having a separate output. I'd let Nikita to
> comment though.

Per my understanding SC7180 has only one DP connected via SS+DP combophy
(At least this is the only thing that is exposed by the QSIP module)

On Aspire 1 the SoC USB0 is hard-wired like so:

  sc7180        USB3 Hub             Type-C DP Switch
--------+     +---------------+    +-----------------+
 SS_TX0 | --> | SS_TX   P1_TX | -> | SS Tx           |
 SS_RX0 | --> | SS_RX   P1_RX | -> | SS Rx     Out   |
        |     +---------------+    |        (4lanes) | ==> [Type-C]
        |                          |                 |
 SS_TX1 | -----------------------> | DP Mux ML1      |
 SS_RX1 | -----------------------> | DP Mux ML0      |
--------+                          +-----------------+

So, basically, the SoC combphy is assumed to do 2+2 DP alt mode in
primary orientation, and the actual orientation switching is done
by a separate DP mux/switch (Represented under EC in Aspire 1, there are
multiple chips roughly governed by EC that make it tick)

Currently this is represented by merely connecting the MDSS DP to
the EC node directly (to represent the link between TX/RX1 and Switch)
where the EC node implements a bridge injecting the HPD signal, which
I assume worked out because the combphy driver so far just hardocded
the correct 2+2 config by default.

However if we want to rope in combphy into this (which I guess we want
to actually configure combphy and not assume it works), we'd want to
connect mdss to combphy and combphy to EC at least in Aspire 1 case.


Nikita


> 
> For the patch:
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> 
> 
>> Take the creative liberty to add a newline before its ports' subnodes
>> though.
>> 
>> [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/
>> 
>> Suggested-by: Rob Herring (Arm) <robh@...nel.org>
>> Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 48 insertions(+)
>>