linux-kernel - Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

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Message-ID: <hjey4kizoizskf3cdcfko2jao2zd3aqpobk35hxsepxqy57p77@jzmldv5ieu3o>
Date: Mon, 11 Aug 2025 17:28:29 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Nikita Travkin <nikita@...n.ru>
Cc: Konrad Dybcio <konradybcio@...nel.org>,
        cros-qcom-dts-watchers@...omium.org,
        Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent
 data paths

On Sat, Aug 09, 2025 at 02:43:47PM +0500, Nikita Travkin wrote:
> Dmitry Baryshkov писал(а) 09.08.2025 12:49:
> > On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
> >> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> >> 
> >> Define ports {} for the DWC controller & the QMPPHY and connect them
> >> together for the SS lanes.
> >> 
> >> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
> >> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
> > 
> > If I remember correctly, on SC7180 the DP is still routed through USB+DP
> > combo PHY rather than having a separate output. I'd let Nikita to
> > comment though.
> 
> Per my understanding SC7180 has only one DP connected via SS+DP combophy
> (At least this is the only thing that is exposed by the QSIP module)
> 
> On Aspire 1 the SoC USB0 is hard-wired like so:
> 
>   sc7180        USB3 Hub             Type-C DP Switch
> --------+     +---------------+    +-----------------+
>  SS_TX0 | --> | SS_TX   P1_TX | -> | SS Tx           |
>  SS_RX0 | --> | SS_RX   P1_RX | -> | SS Rx     Out   |
>         |     +---------------+    |        (4lanes) | ==> [Type-C]
>         |                          |                 |
>  SS_TX1 | -----------------------> | DP Mux ML1      |
>  SS_RX1 | -----------------------> | DP Mux ML0      |
> --------+                          +-----------------+
> 
> So, basically, the SoC combphy is assumed to do 2+2 DP alt mode in
> primary orientation, and the actual orientation switching is done
> by a separate DP mux/switch (Represented under EC in Aspire 1, there are
> multiple chips roughly governed by EC that make it tick)
> 
> Currently this is represented by merely connecting the MDSS DP to
> the EC node directly (to represent the link between TX/RX1 and Switch)
> where the EC node implements a bridge injecting the HPD signal, which
> I assume worked out because the combphy driver so far just hardocded
> the correct 2+2 config by default.
> 
> However if we want to rope in combphy into this (which I guess we want
> to actually configure combphy and not assume it works), we'd want to
> connect mdss to combphy and combphy to EC at least in Aspire 1 case.

Yes, please (especially as you have hardware to test). I'd really prefer
to have DP being connected to the combo PHY (as all other platforms do)
and then we can manually /delete-property/ orientation-switch inside
boards's DT (as it is not being used for switching).

We have a way to describe onboard HUB connections (see the second USB-C
connector on C630).

-- 
With best wishes
Dmitry