linux-kernel - Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

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Message-ID: <y6b5yqjbaz3sya5jg5fmcgivprtybj43eylpftd6z3mamrb737@kua5xzfonnpt>
Date: Mon, 11 Aug 2025 10:11:12 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>
Cc: cros-qcom-dts-watchers@...omium.org, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Marijn Suijten <marijn.suijten@...ainline.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent
 data paths

On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> 
> Define ports {} for the DWC controller & the QMPPHY and connect them
> together for the SS lanes.

Sounds quite reasonable to me, but I can only guess why you think it's a
good idea. Please start with a paragraph documenting which problem
you're solving.

Regards,
Bjorn

> 
> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
> Take the creative liberty to add a newline before its ports' subnodes
> though.
> 
> [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/
> 
> Suggested-by: Rob Herring (Arm) <robh@...nel.org>
> Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 8f827f1d8515d6113c85a2ecacf7ac364e195242..a0df10a97c7f8aa5cd468c8983e74256490d1d06 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -2897,6 +2897,31 @@ usb_1_qmpphy: phy@...8000 {
>  
>  			#clock-cells = <1>;
>  			#phy-cells = <1>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					usb_1_qmpphy_out: endpoint { };
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					usb_1_qmpphy_usb_ss_in: endpoint {
> +						remote-endpoint = <&usb_1_dwc3_ss>;
> +					};
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +
> +					usb_1_qmpphy_dp_in: endpoint { };
> +				};
> +			};
>  		};
>  
>  		pmu@...6300 {
> @@ -3070,6 +3095,26 @@ usb_1_dwc3: usb@...0000 {
>  				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
>  				phy-names = "usb2-phy", "usb3-phy";
>  				maximum-speed = "super-speed";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						usb_1_dwc3_hs: endpoint {
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						usb_1_dwc3_ss: endpoint {
> +							remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
> +						};
> +					};
> +				};
>  			};
>  		};
>  
> @@ -3384,8 +3429,10 @@ mdss_dp: displayport-controller@...0000 {
>  				ports {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> +
>  					port@0 {
>  						reg = <0>;
> +
>  						dp_in: endpoint {
>  							remote-endpoint = <&dpu_intf0_out>;
>  						};
> @@ -3393,6 +3440,7 @@ dp_in: endpoint {
>  
>  					port@1 {
>  						reg = <1>;
> +
>  						mdss_dp_out: endpoint { };
>  					};
>  				};
> 
> ---
> base-commit: b1549501188cc9eba732c25b033df7a53ccc341f
> change-id: 20250808-topic-7180_qmpphy_ports-e63404331685
> 
> Best regards,
> -- 
> Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>