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Message-ID: <ejua4dgtdtlpr22xio6sywhaiyfjrjwdf744s73fz4zxhxyhrk@ep7o37hzwzvv>
Date: Mon, 11 Aug 2025 23:11:12 +0200
From: Uwe Kleine-König <ukleinek@...nel.org>
To: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	Frank.Li@....com, linux-pwm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Ghennadi.Procopciuc@....com, s32@....com
Subject: Re: [PATCH v1 2/2] pwm: Add the S32G support in the Freescale FTM
 driver

Hello Daniel,

On Mon, Aug 11, 2025 at 11:44:32AM +0200, Daniel Lezcano wrote:
> On 11/08/2025 07:18, Uwe Kleine-König wrote:
> > All variants (up to now) have .has_fltctrl == .has_fltpol. Is there a
> > good reason that justifies two bools for the register description?
> 
> Yeah, I agree it can be folded into a single has_flt_reg boolean. I can only
> guess that was done with the idea of sticking to the reference manual and
> perhaps having more variant to come with, eg.,  fltctrl=false and
> fltpol=true
> 
> Do you want me to merge these boolean ?

That's the obvious thing to do if you want the new variant supported :-)

Unless you know that there is such a variant with .has_fltctrl !=
.has_fltpol to appear soon, I prefer the simplified handling with only
one bool.

> > Also I wonder about the fuss given that the two registers are not used
> > in the PWM driver. So this is only to prevent reading these registers
> > via regmap debug stuff? What happens if the memory locations are read
> > where the other implementations have these registers?
> 
> The problem arises at resume time.
> 
> 	/* restore all registers from cache */
>         clk_prepare(fpc->ipg_clk);
> 	regcache_cache_only(fpc->regmap, false);
>         regcache_sync(fpc->regmap);
> 
> Without skipping these registers, the kernel crashes on s32g2/3

That's a useful information for the commit log.

Best regards
Uwe

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