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Message-ID: <56c18c70-ebb9-4018-b8b6-9041337bb3c3@rivosinc.com>
Date: Tue, 12 Aug 2025 14:57:02 +0200
From: Clément Léger <cleger@...osinc.com>
To: yunhui cui <cuiyunhui@...edance.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Himanshu Chauhan <hchauhan@...tanamicro.com>,
Anup Patel <apatel@...tanamicro.com>, Xu Lu <luxu.kernel@...edance.com>,
Atish Patra <atishp@...shpatra.org>, Björn Töpel
<bjorn@...osinc.com>, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [External] [PATCH v6 3/5] drivers: firmware: add riscv SSE
support
On 12/08/2025 14:54, yunhui cui wrote:
>> &preferred_hart);
>> + if (ret)
>> + goto err_event_free;
>> +
>> + cpu = riscv_hartid_to_cpuid(preferred_hart);
>> + sse_global_event_update_cpu(event, cpu);
>> +
>> + ret = sse_sbi_register_event(event, event->global);
>> + if (ret)
>> + goto err_event_free;
>> +
>> + } else {
>> + sse_on_each_cpu(event, SBI_SSE_EVENT_REGISTER,
>> + SBI_SSE_EVENT_DISABLE);
>> + }
> It is necessary to check the return value; otherwise, the event might
> be passed as a valid value to subsequent logic, such as
> sse_event_enable().
>
>
Hi Yunhui,
Indeed, nice catch. I'll fix that.
Thanks,
Clément
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