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Message-ID: <20250812200344.3253781-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 12 Aug 2025 21:03:32 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 01/13] arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
The RZ/T2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index b16fd9259d8d..8ee88b8e8f33 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -90,6 +90,76 @@ sci0: serial@...05000 {
status = "disabled";
};
+ sci1: serial@...05400 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80005400 0 0x400>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci2: serial@...05800 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80005800 0 0x400>;
+ interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci3: serial@...05c00 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80005c00 0 0x400>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci4: serial@...06000 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80006000 0 0x400>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci5: serial@...05000 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x81005000 0 0x400>;
+ interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
i2c0: i2c@...88000 {
compatible = "renesas,riic-r9a09g077";
reg = <0 0x80088000 0 0x400>;
--
2.50.1
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