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Message-ID: <175503322864.231048.3923613819705551334.b4-ty@kernel.org>
Date: Tue, 12 Aug 2025 16:56:20 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: mturquette@...libre.com,
	sboyd@...nel.org,
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	Varadarajan Narayanan <quic_varada@...cinc.com>
Subject: Re: (subset) [PATCH v7 0/4] Enable cpufreq for IPQ5424
On Mon, 11 Aug 2025 14:39:50 +0530, Varadarajan Narayanan wrote:
> CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support.
> Add support for the APSS PLL, RCG and clock enable for ipq5424.
> The PLL, RCG register space are clubbed. Hence adding new APSS driver
> for both PLL and RCG/CBC control. Also the L3 cache has a separate pll
> modeled as ICC clock. The L3 pll needs to be scaled along with the CPU.
> 
> v7: Fix 'Reviewed-by' placement for bindings patch
>     Use enum instead of clock names for l3 pll
>     Select IPQ_APSS_5424 if IPQ_GCC_5424 is enabled
> 
> [...]
Applied, thanks!
[4/4] arm64: dts: qcom: ipq5424: Enable cpufreq
      commit: 77abf70ee126d40dba9ada0a4ccb4c7743f6a3e6
Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>
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