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Message-ID: <eedd44480a76840e1fec73d4433c772c5bdc7011.camel@icenowy.me>
Date: Thu, 14 Aug 2025 01:16:16 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Drew Fustini <fustini@...nel.org>, Guo Ren <guoren@...nel.org>, Fu Wei
<wefu@...hat.com>, Michael Turquette <mturquette@...libre.com>, Stephen
Boyd <sboyd@...nel.org>
Cc: Michal Wilczynski <m.wilczynski@...sung.com>, Yao Zi
<ziyao@...root.org>, Han Gao <rabenda.cn@...il.com>,
linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix
padctrl0
在 2025-08-14星期四的 01:11 +0800,Icenowy Zheng写道:
> Current ccu_gate implementation does not easily allow gates to be
> clock
> parents because of the waste of struct clk_hw in struct ccu_gate;
> however it's found that the padctrl0 apb clock gate seems to be
> downstream of perisys-apb4-hclk, gating the latter w/o gating the
> former
> makes the padctrl0 registers inaccessible too.
>
> Fix this by refactor ccu_gate code, mimicing what Yao Zi did on
> ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus
> gate.
Forgot to mention a easy test of this patchset:
Just install `gpioset` from `libgpiod` on a Lichee Pi 4A, plug a fan to
its fan port, and run `gpioset 3 3=1`. The expected behavior is the fan
starts to spin (because GPIO3_3 is the pin controlling the fan),
however without this patchset Linux will fail to switch that pin.
>
> This patchset depends on the display clock patchset at [1], although
> a
> rebasing to get rid of this dependency is possible.
>
> [1]
> https://lore.kernel.org/linux-riscv/20250813072702.2176993-1-uwu@icenowy.me/
>
> Icenowy Zheng (2):
> clk: thead: th1520-ap: describe gate clocks with clk_gate
> clk: thead: th1520-ap: fix parent of padctrl0 clock
>
> drivers/clk/thead/clk-th1520-ap.c | 385 +++++++++++++++-------------
> --
> 1 file changed, 188 insertions(+), 197 deletions(-)
>
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