lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <aJ4ox8+OLhIir2bU@lizhi-Precision-Tower-5810>
Date: Thu, 14 Aug 2025 14:19:51 -0400
From: Frank Li <Frank.li@....com>
To: James Clark <james.clark@...aro.org>
Cc: Mark Brown <broonie@...nel.org>, Clark Wang <xiaoning.wang@....com>,
	Fugang Duan <B38611@...escale.com>, Gao Pan <pandy.gao@....com>,
	Fugang Duan <fugang.duan@....com>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Larisa Grigore <larisa.grigore@....nxp.com>,
	Larisa Grigore <larisa.grigore@....com>,
	Ghennadi Procopciuc <ghennadi.procopciuc@....com>,
	Ciprianmarian Costea <ciprianmarian.costea@....com>, s32@....com,
	linux-spi@...r.kernel.org, imx@...ts.linux.dev,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 12/13] dt-bindings: lpspi: Document nxp,lpspi-pincfg
 property

On Thu, Aug 14, 2025 at 05:06:52PM +0100, James Clark wrote:
> Document the two valid pincfg values and the defaults.
>
> Although the hardware supports two more values for half-duplex modes,
> the driver doesn't support them so don't document them.

binding doc should be first patch before drivers.

binding descript hardware not driver, you should add all regardless if
driver support it.

>
> Signed-off-by: James Clark <james.clark@...aro.org>
> ---
>  Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> index ce7bd44ee17e..3f8833911807 100644
> --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
> @@ -70,6 +70,19 @@ properties:
>    power-domains:
>      maxItems: 1
>
> +  nxp,pincfg:
> +    description:
> +      'Pin configuration value for CFGR1.PINCFG.
> +        - "sin-in-sout-out": SIN is used for input data and SOUT is used for
> +                             output data
> +        - "sout-in-sin-out": SOUT is used for input data and SIN is used for
> +                             output data
> +      If no value is specified then the default is "sin-in-sout-out" for host
> +      mode and "sout-in-sin-out" for target mode.'

why need this? are there varible at difference boards? look like default
is more make sense.

SPI signal name is MOSI and MISO

Frank

> +    enum:
> +      - sin-in-sout-out
> +      - sout-in-sin-out
> +
>  required:
>    - compatible
>    - reg
> @@ -95,4 +108,5 @@ examples:
>          spi-slave;
>          fsl,spi-only-use-cs1-sel;
>          num-cs = <2>;
> +        nxp,pincfg = "sout-in-sin-out";
>      };
>
> --
> 2.34.1
>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ