linux-kernel - Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5

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Message-ID: <eaafc695-642c-f2db-3745-d17375365621@quicinc.com>
Date: Thu, 14 Aug 2025 10:49:52 +0530
From: Vikash Garodia <quic_vgarodia@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
CC: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski@...aro.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Prakash Gupta <quic_guptap@...cinc.com>
Subject: Re: [PATCH RFC v2 1/3] arm64: dts: qcom: sm8750: Add Iris VPU v3.5



On 8/14/2025 12:11 AM, Dmitry Baryshkov wrote:
> On Tue, Aug 12, 2025 at 09:01:36PM +0530, Vikash Garodia wrote:
>>
>> On 8/12/2025 8:09 PM, Dmitry Baryshkov wrote:
>>> On Tue, Aug 12, 2025 at 04:21:12PM +0200, Konrad Dybcio wrote:
>>>> On 8/6/25 2:38 PM, Krzysztof Kozlowski wrote:
>>>>> Add Iris video codec to SM8750 SoC, which comes with significantly
>>>>> different powering up sequence than previous SM8650, thus different
>>>>> clocks and resets.  For consistency keep existing clock and clock-names
>>>>> naming, so the list shares common part.
>>>>>
>>>>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>>>>>
>>>>> ---
>>>>
>>>> [...]
>>>>
>>>>> +			iris_opp_table: opp-table {
>>>>> +				compatible = "operating-points-v2";
>>>>> +
>>>>> +				opp-240000000 {
>>>>> +					opp-hz = /bits/ 64 <240000000>;
>>>>> +					required-opps = <&rpmhpd_opp_low_svs_d1>,
>>>>> +							<&rpmhpd_opp_low_svs_d1>;
>>>>> +				};
>>>>> +
>>>>> +				opp-338000000 {
>>>>> +					opp-hz = /bits/ 64 <338000000>;
>>>>> +					required-opps = <&rpmhpd_opp_low_svs>,
>>>>> +							<&rpmhpd_opp_low_svs>;
>>>>> +				};
>>>>> +
>>>>> +				opp-420000000 {
>>>>> +					opp-hz = /bits/ 64 <420000000>;
>>>>> +					required-opps = <&rpmhpd_opp_svs>,
>>>>> +							<&rpmhpd_opp_svs>;
>>>>> +				};
>>>>> +
>>>>> +				opp-444000000 {
>>>>> +					opp-hz = /bits/ 64 <444000000>;
>>>>> +					required-opps = <&rpmhpd_opp_svs_l1>,
>>>>> +							<&rpmhpd_opp_svs_l1>;
>>>>> +				};
>>>>> +
>>>>> +				opp-533333334 {
>>>>> +					opp-hz = /bits/ 64 <533333334>;
>>>>> +					required-opps = <&rpmhpd_opp_nom>,
>>>>> +							<&rpmhpd_opp_nom>;
>>>>> +				};
>>>>
>>>> There's an additional OPP: 570 MHz @ NOM_L1
>>>>
>>>> +Dmitry, Vikash, please make sure you're OK with the iommu entries
>>>
>>> We still don't have a way to describe it other way at this point.
>>
>> I could validate the extended "iommu-map-masks" proposal. Given that we have a
> 
> Was it posted? If not, let's get it ASAP.

iommu-range (+Prakash) is a WIP, which is needed alognwith iommu-map-mask.

> 
>> new binding for SM8750 [1] , does it make sense to add iommus min/max as [1,5] ?
> 
> Why [1, 5]? It should be [1, 2] or just [1, 1] + your proposal.

[1,2] should be good for the iris device and remaining SIDs can be covered with
device allocated dynamically via iommu-map-mask proposal

> 
>> such that later if new property is introduced "iommu-map-mask", it does not
>> break ABI.
>>
>> iommus = <&apps_smmu 0x1940 0>;
>> iommu-map-masks = <0 &apps_smmu 0x1947 1 0>;
>>
>> [1] https://lore.kernel.org/all/20250804-sm8750-iris-v2-1-6d78407f8078@linaro.org/
>>
>> Regards,
>> Vikash
>>>
>>>>
>>>> the other properties look OK
>>>>
>>>> Konrad
>>>
>