linux-kernel - Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

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Message-ID: <3da37a91-9512-405b-ba74-c1feb80b4dd2@linaro.org>
Date: Thu, 14 Aug 2025 11:52:58 +0100
From: James Clark <james.clark@...aro.org>
To: Mike Leach <mike.leach@...aro.org>
Cc: Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>,
 kernel@....qualcomm.com, coresight@...ts.linaro.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 Suzuki K Poulose <suzuki.poulose@....com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Subject: Re: [PATCH v2] coresight-etm4x: Conditionally access register
 TRCEXTINSELR



On 14/08/2025 11:25 am, Mike Leach wrote:
> On Thu, 14 Aug 2025 at 10:51, James Clark <james.clark@...aro.org> wrote:
>>
>>
>>
>> On 12/08/2025 9:24 am, Yuanfang Zhang wrote:
>>> The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
>>> To avoid invalid accesses, introduce a check on numextinsel
>>> (derived from TRCIDR5[11:9]) before reading or writing to this register.
>>>
>>> Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses")
>>
>> This tag isn't right. Although this is where the register accesses were
>> last touched, the root issue was present from the introduction of the
>> driver.
>>
> 
> Memory mapped access to unimplemented registers are RES0 so won't fail
> - the issue is the system register access where an undefined exception
> can be triggered.
> 
> Mike
> 

Ah, good point. I assumed that commit was just a refactor.