linux-kernel - Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

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Message-ID: <175680388753.1463011.11768877299078508774.b4-ty@arm.com>
Date: Tue,  2 Sep 2025 10:07:07 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Mike Leach <mike.leach@...aro.org>,
	James Clark <james.clark@...aro.org>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
	kernel@....qualcomm.com,
	coresight@...ts.linaro.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR


On Tue, 12 Aug 2025 01:24:45 -0700, Yuanfang Zhang wrote:
> The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
> To avoid invalid accesses, introduce a check on numextinsel
> (derived from TRCIDR5[11:9]) before reading or writing to this register.
> 
>

The patch looks good to me. May be we could expose this via sysfs, like we
do for the other fields. That can be a separate patch without the Fixes tag.

I have applied this patch to -next, thanks!

[1/1] coresight-etm4x: Conditionally access register TRCEXTINSELR
      https://git.kernel.org/coresight/c/fa71e9cb4cfa

Best regards,
-- 
Suzuki K Poulose <suzuki.poulose@....com>