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Message-ID: <aJ9keuX9ul1Awowy@lizhi-Precision-Tower-5810>
Date: Fri, 15 Aug 2025 12:46:50 -0400
From: Frank Li <Frank.li@....com>
To: Peng Fan <peng.fan@....com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
	imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, Luke Wang <ziniu.wang_1@....com>
Subject: Re: [PATCH 13/13] arm64: dts: imx95-15x15-evk: Change pinctrl
 settings for usdhc2

On Fri, Aug 15, 2025 at 05:03:59PM +0800, Peng Fan wrote:
> From: Luke Wang <ziniu.wang_1@....com>
>
> The drive strength is too high for SDR104 mode. Change the drive
> strength to X3 as hardware team recommends.
>
> Signed-off-by: Luke Wang <ziniu.wang_1@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>

Reviewed-by: Frank Li <Frank.Li@....com>
> ---
>  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> index de7f4321e5f9d7d6a6c46741d3710756dd2b69cf..3c23022923e68fe0f5205d322ad6f8834a46dc56 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> @@ -881,12 +881,12 @@ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e
>
>  	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
> -			IMX95_PAD_SD2_CLK__USDHC2_CLK				0x15fe
> -			IMX95_PAD_SD2_CMD__USDHC2_CMD				0x13fe
> -			IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x13fe
> -			IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x13fe
> -			IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x13fe
> -			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x13fe
> +			IMX95_PAD_SD2_CLK__USDHC2_CLK				0x158e
> +			IMX95_PAD_SD2_CMD__USDHC2_CMD				0x138e
> +			IMX95_PAD_SD2_DATA0__USDHC2_DATA0			0x138e
> +			IMX95_PAD_SD2_DATA1__USDHC2_DATA1			0x138e
> +			IMX95_PAD_SD2_DATA2__USDHC2_DATA2			0x138e
> +			IMX95_PAD_SD2_DATA3__USDHC2_DATA3			0x138e
>  			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT			0x51e
>  		>;
>  	};
>
> --
> 2.37.1
>

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