linux-kernel - Re: [PATCH 3/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB

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Message-ID:
 <MAUPR01MB110726155B08B3F8B481F1B86FE34A@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM>
Date: Fri, 15 Aug 2025 11:57:01 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Zixian Zeng <sycamoremoon376@...il.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Inochi Amaoto <inochiama@...il.com>,
 Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
 <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Alexandre Ghiti <alex@...ti.fr>
Cc: devicetree@...r.kernel.org, sophgo@...ts.linux.dev,
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
 Han Gao <rabenda.cn@...il.com>
Subject: Re: [PATCH 3/4] riscv: dts: sophgo: Enable SPI NOR node for
 SG2042_EVB_V1


On 8/13/2025 4:33 PM, Zixian Zeng wrote:
> Enable SPI NOR node for SG2042_EVB_V1 device tree
>
> Signed-off-by: Han Gao <rabenda.cn@...il.com>
> Signed-off-by: Zixian Zeng <sycamoremoon376@...il.com>
> ---
>   arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> index 3320bc1dd2c66ab1a77fce719f145070ad51f297..d447d66177ee5c66b12af2d8ca79a22cc920c666 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
> @@ -238,6 +238,30 @@ &sd {
>   	status = "okay";
>   };
>   
> +&spifmc0 {
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <100000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
> +&spifmc1 {
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <100000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +

Reviewed-by: Chen Wang <unicorn_wang@...look.com>

Thanks,

Chen

>   &uart0 {
>   	pinctrl-0 = <&uart0_cfg>;
>   	pinctrl-names = "default";
>