linux-kernel - Re: [PATCH v2 1/3] dt-bindings: lgm-dma: Added intel,dma-sw-desc property.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <1826bd7a-621d-49d0-b6ff-7ff723ec9f2c@kernel.org>
Date: Fri, 15 Aug 2025 12:40:04 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Yi xin Zhu <yzhu@...linear.com>, "vkoul@...nel.org" <vkoul@...nel.org>,
 "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
 <krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
 "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
 "kees@...nel.org" <kees@...nel.org>,
 "dave.jiang@...el.com" <dave.jiang@...el.com>,
 "av2082000@...il.com" <av2082000@...il.com>,
 "dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
 "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/3] dt-bindings: lgm-dma: Added intel,dma-sw-desc
 property.

On 15/08/2025 12:06, Yi xin Zhu wrote:
> Hi Krzysztof,
> On 15/08/2025 16:32, Krzysztof wrote:
>>
>>
>> And how is it not a OS policy? Bring reasoning and arguments, otherwise I
>> cannot help you. Your reply above has zero hardware-related arguments, zero
>> facts, zero hardware description.
>>
>> Best regards,
>> Krzysztof
> 
> Let me first describe the DMA hardware capability.  The DMA IP is designed with two control paths.
> 1. Hardware descriptor mode.  The DMA can be connected to another HW component that provides
> Descriptors to DMA to automate DMA transfers.
> 2. Software descriptor mode.  The DMA IP also has interface to CPU via registers to allow CPU to
> manage the DMA transfers.
> 
> Which mode DMA works in depends on SoC level configuration.  In the SoC, it could be some

What is a "SoC level configuration"?

>From your explanation 1+2 it feels like consumer chooses it. Where is a
full DTS showing all this?

> of the DMA instances work in hardware descriptor mode while other DMA instances work in
> software descriptor mode or all in HW/SW mode.
> 

Best regards,
Krzysztof