lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <aKLl010zQ1dFn/bk@intel.com>
Date: Mon, 18 Aug 2025 16:35:31 +0800
From: Chao Gao <chao.gao@...el.com>
To: "Chang S. Bae" <chang.seok.bae@...el.com>
CC: <x86@...nel.org>, <tglx@...utronix.de>, <mingo@...hat.com>,
	<bp@...en8.de>, <dave.hansen@...ux.intel.com>, <colinmitchell@...gle.com>,
	<abusse@...zon.de>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 6/6] x86/microcode/intel: Enable staging when available

On Wed, Aug 13, 2025 at 10:26:49AM -0700, Chang S. Bae wrote:
>With the staging code being ready, check for staging availability by
>reading these following MSRs:
>
>  * IA32_ARCH_CAPABILITIES (bit 16) for the presence of
>    IA32_MCU_ENUMERATION
>
>  * IA32_MCU_ENUMERATION (bit 4) for the staging feature availability.
>
>When available, enable it by setting the feature bit.
>
>Signed-off-by: Chang S. Bae <chang.seok.bae@...el.com>
>Tested-by: Anselm Busse <abusse@...zon.de>

Reviewed-by: Chao Gao <chao.gao@...el.com>

<snip>

>+static __init bool staging_available(void)
>+{
>+	u64 val;
>+
>+	val = x86_read_arch_cap_msr();
>+	if (!(val & ARCH_CAP_MCU_ENUM))
>+		return false;
>+
>+	rdmsrl(MSR_IA32_MCU_ENUMERATION, val);

nit: s/rdmsrl/rdmsrq

rdmsrl has been renamed to rdmsrq.

>+	return !!(val & MCU_STAGING);
>+}
>+

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ