linux-kernel - Re: [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support

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Message-ID: <aKSk8ozFw8wHbSIH@tom-desktop>
Date: Tue, 19 Aug 2025 18:23:14 +0200
From: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
To: Biju <biju.das.au@...il.com>
Cc: Uwe Kleine-König <ukleinek@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>, linux-pwm@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support

Hi Biju,
Thank you for your patch.

On Thu, Aug 14, 2025 at 07:41:09PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
> 
> Add RZ/G3E GPT support. It has multiple clocks and resets compared to
> RZ/G2L. Also prescale field width and factor for calculating prescale
> are different.
> 

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>

> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> ---
>  drivers/pwm/pwm-rzg2l-gpt.c | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index b247a6c181d5..7047359cac63 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -153,6 +153,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
>  	return prescale;
>  }
>  
> +static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks)
> +{
> +	u32 prescaled_period_ticks;
> +	u8 prescale;
> +
> +	prescaled_period_ticks = period_ticks >> 32;
> +	if (prescaled_period_ticks >= 64 && prescaled_period_ticks < 256) {
> +		prescale = 6;
> +	} else if (prescaled_period_ticks >= 256 && prescaled_period_ticks < 1024) {
> +		prescale = 8;
> +	} else if (prescaled_period_ticks >= 1024) {
> +		prescale = 10;
> +	} else {
> +		prescale = fls(prescaled_period_ticks);
> +		if (prescale > 1)
> +			prescale -= 1;
> +	}
> +
> +	return prescale;
> +}
> +
>  static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
>  	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
> @@ -443,6 +464,14 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
>  	if (IS_ERR(rstc))
>  		return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
>  
> +	rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s");
> +	if (IS_ERR(rstc))
> +		return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n");
> +
> +	clk = devm_clk_get_optional_enabled(dev, "bus");
> +	if (IS_ERR(clk))
> +		return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n");
> +
>  	clk = devm_clk_get_enabled(dev, NULL);
>  	if (IS_ERR(clk))
>  		return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
> @@ -481,6 +510,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +static const struct rzg2l_gpt_info rzg3e_data = {
> +	.calculate_prescale = rzg3e_gpt_calculate_prescale,
> +	.gtcr_tpcs_mask = GENMASK(26, 23),
> +	.prescale_pow_of_two_mult_factor = 1,
> +};
> +
>  static const struct rzg2l_gpt_info rzg2l_data = {
>  	.calculate_prescale = rzg2l_gpt_calculate_prescale,
>  	.gtcr_tpcs_mask = GENMASK(26, 24),
> @@ -488,6 +523,7 @@ static const struct rzg2l_gpt_info rzg2l_data = {
>  };
>  
>  static const struct of_device_id rzg2l_gpt_of_table[] = {
> +	{ .compatible = "renesas,r9a09g047-gpt", .data = &rzg3e_data },
>  	{ .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
>  	{ /* Sentinel */ }
>  };
> -- 
> 2.43.0
> 

Thanks & Regards,
Tommaso