[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
<AS8PR04MB8833DF96022E981E2766B9768C30A@AS8PR04MB8833.eurprd04.prod.outlook.com>
Date: Tue, 19 Aug 2025 09:01:04 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Manivannan Sadhasivam <mani@...nel.org>
CC: Frank Li <frank.li@....com>, "l.stach@...gutronix.de"
<l.stach@...gutronix.de>, "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
"kwilczynski@...nel.org" <kwilczynski@...nel.org>, "robh@...nel.org"
<robh@...nel.org>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>, "bhelgaas@...gle.com"
<bhelgaas@...gle.com>, "shawnguo@...nel.org" <shawnguo@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>, "kernel@...gutronix.de"
<kernel@...gutronix.de>, "festevam@...il.com" <festevam@...il.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 1/2] dt-bindings: PCI: dwc: Add vaux regulator
> -----Original Message-----
> From: Manivannan Sadhasivam <mani@...nel.org>
> Sent: 2025年8月19日 16:46
> To: Hongxing Zhu <hongxing.zhu@....com>
> Cc: Frank Li <frank.li@....com>; l.stach@...gutronix.de;
> lpieralisi@...nel.org; kwilczynski@...nel.org; robh@...nel.org;
> krzk+dt@...nel.org; conor+dt@...nel.org; bhelgaas@...gle.com;
> shawnguo@...nel.org; s.hauer@...gutronix.de; kernel@...gutronix.de;
> festevam@...il.com; linux-pci@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; devicetree@...r.kernel.org;
> imx@...ts.linux.dev; linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v4 1/2] dt-bindings: PCI: dwc: Add vaux regulator
>
> On Tue, Aug 19, 2025 at 03:16:29PM GMT, Richard Zhu wrote:
> > Refer to PCIe CEM r6.0, sec 2.3 WAKE# Signal, WAKE# signal is only
> > asserted by the Add-in Card when all its functions are in D3Cold state
> > and at least one of its functions is enabled for wakeup generation.
> >
> > The 3.3V auxiliary power (+3.3Vaux) must be present and used for
> > wakeup process. Since the main power supply would be gated off to let
> > Add-in Card to be in D3Cold, add the vaux and keep it enabled to power
> > up WAKE# circuit for the entire PCIe controller lifecycle when WAKE# is
> supported.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > ---
> > .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 6
> ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > index 34594972d8dbe..5283f51388584 100644
> > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > @@ -262,6 +262,12 @@ properties:
> >
> > dma-coherent: true
> >
> > + vaux-supply:
> > + description: Should specify the regulator in charge of power source
> > + of the WAKE# generation on the PCIe connector. When the WAKE#
> is
> > + enabled, this regualor would be always on and used to power up
> > + WAKE# circuit.
>
> 3.3Vaux supply is already documented in the dtschema:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Fdevicetree-org%2Fdt-schema%2Fblob%2Fmain%2Fdtschema%2Fsche
> mas%2Fpci%2Fpci-bus-common.yaml%23L179&data=05%7C02%7Chongxing.z
> hu%40nxp.com%7C010fb118c1384dfa2b1a08dddefcd0ff%7C686ea1d3bc2b4c
> 6fa92cd99c5c301635%7C0%7C0%7C638911899600090830%7CUnknown%7CT
> WFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXa
> W4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2Bh
> CgrwfHFGY2D5%2B8dS4XRl4hoQWG0JpUmG5BZhRyW%2B8%3D&reserved=0
>
> So you should use that instead.
Okay, got that, thanks.
Best Regards
Richard Zhu
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
Powered by blists - more mailing lists