linux-kernel - Re: [PATCH v7 4/6] dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N

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Message-ID: <CAMuHMdVFxaCrBu0fAJX3wmY9wdgHn1O8-cVOS6OKN6HGX9v55g@mail.gmail.com>
Date: Tue, 19 Aug 2025 12:40:34 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Andrzej Hajda <andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>, 
	Robert Foss <rfoss@...nel.org>, Laurent Pinchart <Laurent.pinchart@...asonboard.com>, 
	Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>, 
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, 
	Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Biju Das <biju.das.jz@...renesas.com>, Magnus Damm <magnus.damm@...il.com>, 
	dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Tommaso Merciai <tommaso.merciai.xr@...renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, 
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v7 4/6] dt-bindings: display: bridge: renesas,dsi:
 Document RZ/V2H(P) and RZ/V2N

On Mon, 28 Jul 2025 at 22:28, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> On Mon, Jul 28, 2025 at 9:14 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add the compatible string "renesas,r9a09g057-mipi-dsi" for the Renesas
> > RZ/V2H(P) (R9A09G057) SoC. While the MIPI DSI LINK registers are shared
> > with the RZ/G2L SoC, the D-PHY register layout differs. Additionally, the
> > RZ/V2H(P) uses only two resets compared to three on RZ/G2L, and requires
> > five clocks instead of six.
> >
> > To reflect these hardware differences, update the binding schema to
> > support the reduced clock and reset requirements for RZ/V2H(P).
> >
> > Since the RZ/V2N (R9A09G056) SoC integrates an identical DSI IP to
> > RZ/V2H(P), the same "renesas,r9a09g057-mipi-dsi" compatible string is
> > reused for RZ/V2N.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> > ---
> > v6->v7:
> > - Renamed pllclk to pllrefclk
> > - Preserved the reviewed by tag from Geert and Krzysztof
> >
> - Included support for RZ/V2N in the same patch
> - Updated commit description.
>
> I missed mentioning the above.

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds