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Message-Id: <20250820-drm-tidss-field-api-v2-10-43cab671c648@kernel.org>
Date: Wed, 20 Aug 2025 16:01:50 +0200
From: Maxime Ripard <mripard@...nel.org>
To: Jyri Sarha <jyri.sarha@....fi>,
Tomi Valkeinen <tomi.valkeinen@...asonboard.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>
Cc: dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Maxime Ripard <mripard@...nel.org>
Subject: [PATCH v2 10/14] drm/tidss: dispc: Switch VID_REG_FLD_MOD to using
a mask
The VID_REG_FLD_MOD function takes the start and end bits as parameter
and will generate a mask out of them.
This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.
Let's change VID_REG_FLD_MOD to take the mask as an argument instead,
and let the caller create the mask. Eventually, this mask will be moved
to a define.
Signed-off-by: Maxime Ripard <mripard@...nel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index b4928cfbb6f7ca9a03371c5e599e2029baae333f..8c0949203ace147e403ea43ab468c3a56d170156 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -622,17 +622,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
})
#define VID_REG_GET(dispc, hw_plane, idx, mask) \
((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx))))
-#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \
+#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, mask) \
({ \
struct dispc_device *_dispc = (dispc); \
u32 _hw_plane = (hw_plane); \
u32 _idx = (idx); \
u32 _reg = dispc_vid_read(_dispc, _hw_plane, _idx); \
- FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \
+ FIELD_MODIFY((mask), &_reg, (val)); \
dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \
})
#define VP_REG_GET(dispc, vp, idx, start, end) \
((u32)FIELD_GET(GENMASK((start), (end)), \
@@ -1755,11 +1755,12 @@ static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,
}
static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,
bool enable)
{
- VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);
+ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable,
+ GENMASK(9, 9));
}
/* SCALER */
static u32 dispc_calc_fir_inc(u32 in, u32 out)
@@ -2012,24 +2013,24 @@ static void dispc_vid_set_scaling(struct dispc_device *dispc,
u32 hw_plane,
struct dispc_scaling_params *sp,
u32 fourcc)
{
/* HORIZONTAL RESIZE ENABLE */
- VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
- sp->scale_x, 7, 7);
+ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x,
+ GENMASK(7, 7));
/* VERTICAL RESIZE ENABLE */
- VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
- sp->scale_y, 8, 8);
+ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y,
+ GENMASK(8, 8));
/* Skip the rest if no scaling is used */
if (!sp->scale_x && !sp->scale_y)
return;
/* VERTICAL 5-TAPS */
- VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
- sp->five_taps, 21, 21);
+ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps,
+ GENMASK(21, 21));
if (dispc_fourcc_is_yuv(fourcc)) {
if (sp->scale_x) {
dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
sp->fir_xinc_uv);
@@ -2115,11 +2116,11 @@ static void dispc_plane_set_pixel_format(struct dispc_device *dispc,
for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) {
if (dispc_color_formats[i].fourcc == fourcc) {
VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
dispc_color_formats[i].dss_code,
- 6, 1);
+ GENMASK(6, 1));
return;
}
}
WARN_ON(1);
@@ -2293,19 +2294,20 @@ void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
0xFF & (state->alpha >> 8));
if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
- 28, 28);
+ GENMASK(28, 28));
else
VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
- 28, 28);
+ GENMASK(28, 28));
}
void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)
{
- VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
+ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable,
+ GENMASK(0, 0));
}
static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
{
return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS,
@@ -2370,11 +2372,11 @@ static void dispc_k2g_plane_init(struct dispc_device *dispc)
* Prefetch up to fifo high-threshold value to minimize the
* possibility of underflows. Note that this means the PRELOAD
* register is ignored.
*/
VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
- 19, 19);
+ GENMASK(19, 19));
}
}
static void dispc_k3_plane_init(struct dispc_device *dispc)
{
@@ -2421,11 +2423,11 @@ static void dispc_k3_plane_init(struct dispc_device *dispc)
dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
/* Prefech up to PRELOAD value */
VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
- 19, 19);
+ GENMASK(19, 19));
}
}
static void dispc_plane_init(struct dispc_device *dispc)
{
--
2.50.1
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