lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <43bb8dbe-8213-4c12-b9e8-0182f808dd9c@amd.com>
Date: Wed, 20 Aug 2025 09:03:54 +0530
From: "Upadhyay, Neeraj" <neeraj.upadhyay@....com>
To: Borislav Petkov <bp@...en8.de>
Cc: linux-kernel@...r.kernel.org, tglx@...utronix.de, mingo@...hat.com,
 dave.hansen@...ux.intel.com, Thomas.Lendacky@....com, nikunj@....com,
 Santosh.Shukla@....com, Vasant.Hegde@....com, Suravee.Suthikulpanit@....com,
 David.Kaplan@....com, x86@...nel.org, hpa@...or.com, peterz@...radead.org,
 seanjc@...gle.com, pbonzini@...hat.com, kvm@...r.kernel.org,
 kirill.shutemov@...ux.intel.com, huibo.wang@....com, naveen.rao@....com,
 francescolavra.fl@...il.com, tiala@...rosoft.com
Subject: Re: [PATCH v9 03/18] x86/apic: Populate .read()/.write() callbacks of
 Secure AVIC driver



On 8/19/2025 8:02 PM, Borislav Petkov wrote:
> On Tue, Aug 19, 2025 at 09:45:02AM +0530, Upadhyay, Neeraj wrote:
>> Maybe change it to below?
>>
>> /*
>>   * Valid APIC_IRR/SAVIC_ALLOWED_IRR registers are at 16 bytes strides
>>   * from their respective base offset.
>>   */
>>
>> if (WARN_ONCE(!(IS_ALIGNED(reg - APIC_IRR, 16) ||
>>                  IS_ALIGNED(reg - SAVIC_ALLOWED_IRR, 16)),
>>                "Misaligned APIC_IRR/ALLOWED_IRR APIC register read offset
>> 0x%x",
>>                reg))
> 
> Let's beef that up some more with a crystal-clear explanation what is going on
> here so that readers don't have to stop and stare for 5 mins before they grok
> what this is doing:
> 
> 	/*
> 	 * Valid APIC_IRR/SAVIC_ALLOWED_IRR registers are at 16 bytes strides from
> 	 * their respective base offset. APIC_IRRs are in the range
> 	 *
> 	 * (0x200, 0x210,  ..., 0x270)
> 	 *
> 	 * while the SAVIC_ALLOWED_IRR range starts 4 bytes later, in the rangea
> 	 *
> 	 * (0x204, 0x214, ..., 0x274).
> 	 *
> 	 * Filter out everything else.
> 	 */
> 	 if (WARN_ONCE(!(IS_ALIGNED(reg, 16) ||
> 		 	 IS_ALIGNED(reg - 4, 16)),
> 		      "Misaligned APIC_IRR/ALLOWED_IRR APIC register read offset 0x%x", reg));
> 

Ok, looks good. Thanks!


- Neeraj

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ