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Message-ID: <20250821130741.GL802098@nvidia.com>
Date: Thu, 21 Aug 2025 10:07:41 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Nicolin Chen <nicolinc@...dia.com>
Cc: Ethan Zhao <etzhao1900@...il.com>, robin.murphy@....com,
	joro@...tes.org, bhelgaas@...gle.com, will@...nel.org,
	robin.clark@....qualcomm.com, yong.wu@...iatek.com,
	matthias.bgg@...il.com, angelogioacchino.delregno@...labora.com,
	thierry.reding@...il.com, vdumpa@...dia.com, jonathanh@...dia.com,
	rafael@...nel.org, lenb@...nel.org, kevin.tian@...el.com,
	yi.l.liu@...el.com, baolu.lu@...ux.intel.com,
	linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
	linux-mediatek@...ts.infradead.org, linux-tegra@...r.kernel.org,
	linux-acpi@...r.kernel.org, linux-pci@...r.kernel.org,
	patches@...ts.linux.dev, pjaroszynski@...dia.com, vsethi@...dia.com,
	helgaas@...nel.org
Subject: Re: [PATCH v3 5/5] pci: Suspend iommu function prior to resetting a
 device

On Tue, Aug 19, 2025 at 02:59:07PM -0700, Nicolin Chen wrote:
>  c) multiple pci_devs with their own RIDs
> 
>     In this case, either FLR or IOMMU only resets the PF. That
>     being said, VFs might be affected since PF is resetting?
>     If there is an issue, I don't see it coming from the IOMMU-
>     level reset..

It would still allow the ATS issue from the VF side. The VF could be
pushing an invalidation during the PF reset that will get clobbered.

I haven't fully checked but I think Linux doesn't really (easially?)
allow resetting a PF while a VF is present...

Arguably if the PF is reset the VFs should have their translations
blocked too.

Jason

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