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Message-ID: <25140dcc-fcd5-476f-8c26-7e99c7381552@roeck-us.net>
Date: Wed, 20 Aug 2025 20:50:00 -0700
From: Guenter Roeck <linux@...ck-us.net>
To: Prabhakar <prabhakar.csengg@...il.com>,
Wim Van Sebroeck <wim@...ux-watchdog.org>, Rob Herring <robh@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>,
Magnus Damm <magnus.damm@...il.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>
Cc: linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v4 1/6] dt-bindings: watchdog: renesas,wdt: Add support
for RZ/T2H and RZ/N2H
On 8/20/25 13:23, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Extend the Renesas WDT device tree bindings to support the watchdog timer
> found on the RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
>
> The RZ/T2H WDT is mostly compatible with the one found on the RZ/V2H(P),
> but includes an additional register and differs in the clock division
> ratio settings for the WDTCR[CKS] field. To reflect these differences,
> introduce a new compatible string, "renesas,r9a09g077-wdt".
>
> The binding schema is updated accordingly. On RZ/T2H, the WDT does not
> require the "resets" property. It also requires two register regions and
> the presence of a "power-domains" property. The "clock-names" property is
> limited to a single entry, "pclk", for this SoC.
>
> The RZ/N2H SoC uses the same WDT IP as the RZ/T2H. It is supported by
> using "renesas,r9a09g087-wdt" as the primary compatible string, with
> "renesas,r9a09g077-wdt" listed as a fallback to describe the shared
> hardware features.
>
> Example:
> wdt0: watchdog@...82000 {
> compatible = "renesas,r9a09g077-wdt";
> reg = <0 0x80082000 0 0x400>,
> <0 0x81295100 0 0x04>;
> clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
> clock-names = "pclk";
> power-domains = <&cpg>;
> status = "disabled";
> };
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Reviewed-by: Guenter Roeck <linux@...ck-us.net>
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