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Message-ID: <2635ced4-b91f-4c79-ae2a-079f06bbb8a9@quicinc.com>
Date: Fri, 22 Aug 2025 14:53:31 +0530
From: Nitin Rawat <quic_nitirawa@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
        "Manivannan
 Sadhasivam" <mani@...nel.org>
CC: <vkoul@...nel.org>, <kishon@...nel.org>, <andersson@...nel.org>,
        <konradybcio@...nel.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V3 2/2] phy: qcom-qmp-ufs: Add regulator loads for SM8650
 and SM8750



On 8/22/2025 2:45 PM, Dmitry Baryshkov wrote:
> On 22/08/2025 11:53, Manivannan Sadhasivam wrote:
>> On Wed, Aug 20, 2025 at 03:49:31AM GMT, Dmitry Baryshkov wrote:
>>> On Wed, Aug 20, 2025 at 03:58:26AM +0530, Nitin Rawat wrote:
>>>> Add regulator load voting support for SM8650 and SM8750 platforms by
>>>> introducing dedicated regulator bulk data arrays with their load
>>>> values.
>>>>
>>>> The load requirements are:
>>>> - SM8650: vdda-phy (205mA), vdda-pll (17.5mA)
>>>> - SM8750: vdda-phy (213mA), vdda-pll (18.3mA)
>>>>
>>>> This ensures stable operation and proper power management for these
>>>> platforms where regulators are shared between the QMP USB PHY and
>>>> other IP blocks by setting appropriate regulator load currents 
>>>> during PHY
>>>> operations.
>>>>
>>>> Configurations without specific load requirements will continue to work
>>>> unchanged, as init_load_uA remains zero-initialized when .init_load_uA
>>>> is not provided.
>>>
>>> Can we please get configuration for the rest of the platforms?
>>>
>>
>> Only if the rest of the platforms require setting the load... It is 
>> not very
>> clear if the older platforms share the regulators with other IPs or not.
> 
> Yes, they are usually shared. USB. PCIe and DSI frequently sit on the 
> same voltage rails.

Yes, it’s typically shared across multiple clients.

However, as I mentioned earlier, in the current upstream codebase, the 
"regulator-allow-set-load" property is defined only for SM8750 and 
SM8650 within the PMIC PHY and PLL device tree nodes. This means that 
even if the UFS PHY driver is updated to vote for this configuration on 
other platforms, it will have no effect, as the property is not 
supported there.


> 
> 


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