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Message-ID: <20250823155214.17465-1-chang.seok.bae@intel.com>
Date: Sat, 23 Aug 2025 08:52:03 -0700
From: "Chang S. Bae" <chang.seok.bae@...el.com>
To: linux-kernel@...r.kernel.org
Cc: x86@...nel.org,
tglx@...utronix.de,
mingo@...hat.com,
bp@...en8.de,
dave.hansen@...ux.intel.com,
chao.gao@...el.com,
abusse@...zon.de,
chang.seok.bae@...el.com
Subject: [PATCH v5 0/7] x86: Support for Intel Microcode Staging Feature
Hi all,
This is another iteration -- changes since v4 [*]:
* Reworked the preparatory change before referencing
cpu_primary_thread_mask, based on Dave’s feedback. This is now patch1.
* Incorporated further feedback from Dave on the staging code, mainly
to improve clarity, reduce ambiguity, and fix minor issues. Each
patch includes some details.
* Collected Chao’s review tag (thanks!) for the first and last patches.
As usual, the series is also available here:
git://github.com/intel-staging/microcode.git staging_v5
[*] https://lore.kernel.org/lkml/20250813172649.15474-1-chang.seok.bae@intel.com/
Thanks,
Chang
Chang S. Bae (7):
x86/cpu/topology: Make primary thread mask available with SMP=n
x86/microcode: Introduce staging step to reduce late-loading time
x86/microcode/intel: Establish staging control logic
x86/microcode/intel: Define staging state struct
x86/microcode/intel: Implement staging handler
x86/microcode/intel: Support mailbox transfer
x86/microcode/intel: Enable staging when available
arch/x86/include/asm/msr-index.h | 9 +
arch/x86/include/asm/topology.h | 12 +-
arch/x86/kernel/cpu/microcode/core.c | 11 +
arch/x86/kernel/cpu/microcode/intel.c | 386 +++++++++++++++++++++++
arch/x86/kernel/cpu/microcode/internal.h | 4 +-
arch/x86/kernel/cpu/topology.c | 4 -
arch/x86/kernel/cpu/topology_common.c | 3 +
arch/x86/kernel/smpboot.c | 3 -
8 files changed, 418 insertions(+), 14 deletions(-)
base-commit: 7182bf4176f93be42225d2ef983894febfa4a1b1
--
2.48.1
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