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Message-ID: <aKn6AYIAG9eUeSx2@codespaces-a28d22>
Date: Sat, 23 Aug 2025 17:27:29 +0000
From: Denzeel Oliva <wachiturroxd150@...il.com>
To: Conor Dooley <conor@...nel.org>
Cc: Krzysztof Kozlowski <krzk@...nel.org>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Alim Akhtar <alim.akhtar@...sung.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks
and extend
> This looks like a massive ABI break, where is the justification for
> doing it?
>
> Cheers,
> Conor.
Hi Conor,
I reordered because the current IDs don’t match CMU_TOP:
the PLL mux select is in PLL_CON0, not CON3, which gave wrong/low rates.
I also added DPU/CMUREF and a missing fixed-factor path to stop bad rates
and clk_summary hangs on hardware.
I’d rather fix the mapping now than keep a wrong layout.
Thanks,
Denzeel
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