linux-kernel - RE: [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

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Message-ID:
 <ZQ2PR01MB1307F15B7A9D4E8EF6319837E63C2@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn>
Date: Sat, 23 Aug 2025 17:36:09 +0000
From: Hal Feng <hal.feng@...rfivetech.com>
To: E Shattow <e@...eshell.de>, Emil Renner Berthing <kernel@...il.dk>, Conor
 Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
	<krzk+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer
 Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Alexandre
 Ghiti <alex@...ti.fr>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram
 hinting needed by boot loader

> On 23.08.25 18:02, E Shattow wrote:
> Add bootph-pre-ram hinting to jh7110.dtsi:
>   - CPU interrupt controller(s)
>   - gmac1_rgmii_rxin fixed-clock (dependency of syscrg)
>   - gmac1_rmii_refin fixed-clock (dependency of syscrg)
>   - oscillator
>   - core local interrupt timer
>   - syscrg clock-controller
>   - pllclk clock-controller (dependency of syscrg)
>   - DDR memory controller
> 
> Signed-off-by: E Shattow <e@...eshell.de>

Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>

Best regards,
Hal

> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index f3876660c07f..6e56e9d20bb0 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -35,6 +35,7 @@ S7_0: cpu@0 {
> 
>  			cpu0_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -68,6 +69,7 @@ U74_1: cpu@1 {
> 
>  			cpu1_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -101,6 +103,7 @@ U74_2: cpu@2 {
> 
>  			cpu2_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -134,6 +137,7 @@ U74_3: cpu@3 {
> 
>  			cpu3_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -167,6 +171,7 @@ U74_4: cpu@4 {
> 
>  			cpu4_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock {
> 
>  	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
>  		compatible = "fixed-clock";
> +		bootph-pre-ram;
>  		clock-output-names = "gmac1_rgmii_rxin";
>  		#clock-cells = <0>;
>  	};
> 
>  	gmac1_rmii_refin: gmac1-rmii-refin-clock {
>  		compatible = "fixed-clock";
> +		bootph-pre-ram;
>  		clock-output-names = "gmac1_rmii_refin";
>  		#clock-cells = <0>;
>  	};
> @@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock {
> 
>  	osc: oscillator {
>  		compatible = "fixed-clock";
> +		bootph-pre-ram;
>  		clock-output-names = "osc";
>  		#clock-cells = <0>;
>  	};
> @@ -354,6 +362,7 @@ soc {
>  		clint: timer@...0000 {
>  			compatible = "starfive,jh7110-clint", "sifive,clint0";
>  			reg = <0x0 0x2000000 0x0 0x10000>;
> +			bootph-pre-ram;
>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
> 7>,
>  					      <&cpu1_intc 3>, <&cpu1_intc 7>,
>  					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> @@ -880,6 +889,7 @@ qspi: spi@...10000 {
>  		syscrg: clock-controller@...20000 {
>  			compatible = "starfive,jh7110-syscrg";
>  			reg = <0x0 0x13020000 0x0 0x10000>;
> +			bootph-pre-ram;
>  			clocks = <&osc>, <&gmac1_rmii_refin>,
>  				 <&gmac1_rgmii_rxin>,
>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, @@ -
> 904,6 +914,7 @@ sys_syscon: syscon@...30000 {
> 
>  			pllclk: clock-controller {
>  				compatible = "starfive,jh7110-pll";
> +				bootph-pre-ram;
>  				clocks = <&osc>;
>  				#clock-cells = <1>;
>  			};
> @@ -935,6 +946,7 @@ memory-controller@...00000 {
>  			compatible = "starfive,jh7110-dmc";
>  			reg = <0x0 0x15700000 0x0 0x10000>,
>  			      <0x0 0x13000000 0x0 0x10000>;
> +			bootph-pre-ram;
>  			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
>  			clock-names = "pll";
>  			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> --
> 2.50.0