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Message-ID:
<ZQ2PR01MB1307D52CDAE655997B6AF864E63C2@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn>
Date: Sat, 23 Aug 2025 17:34:20 +0000
From: Hal Feng <hal.feng@...rfivetech.com>
To: E Shattow <e@...eshell.de>, Emil Renner Berthing <kernel@...il.dk>, Conor
Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer
Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Alexandre
Ghiti <alex@...ti.fr>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory
controller
> On 23.08.25 18:02, E Shattow wrote:
>
> Add JH7110 SoC DDR external memory controller.
>
> Signed-off-by: E Shattow <e@...eshell.de>
Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
Best regards,
Hal
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0ba74ef04679..f3876660c07f 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -931,6 +931,18 @@ watchdog@...70000 {
> <&syscrg JH7110_SYSRST_WDT_CORE>;
> };
>
> + memory-controller@...00000 {
> + compatible = "starfive,jh7110-dmc";
> + reg = <0x0 0x15700000 0x0 0x10000>,
> + <0x0 0x13000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> + clock-names = "pll";
> + resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> + <&syscrg JH7110_SYSRST_DDR_OSC>,
> + <&syscrg JH7110_SYSRST_DDR_APB>;
> + reset-names = "axi", "osc", "apb";
> + };
> +
> crypto: crypto@...00000 {
> compatible = "starfive,jh7110-crypto";
> reg = <0x0 0x16000000 0x0 0x4000>;
> --
> 2.50.0
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