linux-kernel - Re: [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <aKx5iFEXVGlzWETl@lx-t490>
Date: Mon, 25 Aug 2025 16:56:08 +0200
From: "Ahmed S. Darwish" <darwi@...utronix.de>
To: Borislav Petkov <bp@...en8.de>
Cc: Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Andrew Cooper <andrew.cooper3@...rix.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	David Woodhouse <dwmw2@...radead.org>,
	Sean Christopherson <seanjc@...gle.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Sohil Mehta <sohil.mehta@...el.com>,
	John Ogness <john.ogness@...utronix.de>, x86@...nel.org,
	x86-cpuid@...ts.linux.dev, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf_types.h>

Hi Boris,

On Mon, 25 Aug 2025, Borislav Petkov wrote:
>
> On Fri, Aug 15, 2025 at 09:01:59AM +0200, Ahmed S. Darwish wrote:
> > +struct leaf_0x1_0 {
> > +	// eax
> > +	u32	stepping			:  4, // Stepping ID
>
> All those bit names in all those leafs: are they taken from the official
> documentation?
>

Yes, I've built the 86-cpuid-db XML database from the official sources.

Intel:

    Intel® 64 and IA-32 Architectures Software Developer's Manual
    Intel® Architecture Instruction Set Extensions and Future Features
    Intel® CPUID Enumeration and Architectural MSRs
    Intel® X86-S External Architectural Specification
    Intel® Key Locker Specification
    Intel® Architecture Memory Encryption Technologies Specification
    Intel® Trust Domain CPU Architectural Extensions
    Intel® Architecture Specification: Intel® Trust Domain Extensions (TDX)
    Intel® Flexible Return and Event Delivery (FRED) Specification

AMD:

    AMD64 Architecture Programmer’s Manual, Volumes 1–5
    Preliminary Processor Programming Reference (PPR) for AMD Family 19h
    Model 11h, Revision B1 Processors
    Open-Source Register Reference For AMD Family 17h Processors Models 00h-2Fh

Transmeta:

    Processor Recognition, Transmeta Corporation (2002/05/07)

This is also listed under the 'References' section of the project:

    https://gitlab.com/x86-cpuid.org/x86-cpuid-db

There are some bitfields contributed by Intel and AMD developers that are
not yet in the official documentation.  In such cases, I trusted that
such info is posted from developers within Intel and/or AMD.

>
> > +/*
> > + * Leaf 0x5
> > + * MONITOR/MWAIT instructions enumeration
> 				 ^^^^^^^^^^^
> Let's drop all those tautologies - it is absolutely clear that it is an
> enumeration so no need for it. Just keep the minimum text that is needed to
> describe the bit. People can always use that to find the official
> documentation of they need more info.
>

will do.

>
> > +/*
> > + * Leaf 0x18
> > + * Intel determenestic address translation (TLB) parameters
>
> + * Intel determenestic address translation (TLB) parameters
> Unknown word [determenestic] in comment.
> Suggestions: ['deterministic',...
>
> spellchecker please.
>

will do.

[ I have a spellcheck CI pipeline for the XML database, but somehow I
  missed checking the leaf description field :( ]

Thanks!

--
Ahmed S. Darwish
Linutronix GmbH