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Message-ID:
<ZQ2PR01MB130747BFF530B0EF64C5D833E63E2@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn>
Date: Mon, 25 Aug 2025 03:20:03 +0000
From: Hal Feng <hal.feng@...rfivetech.com>
To: E Shattow <e@...eshell.de>, Conor Dooley <conor+dt@...nel.org>, Emil
Renner Berthing <emil.renner.berthing@...onical.com>, Heinrich Schuchardt
<heinrich.schuchardt@...onical.com>, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Palmer Dabbelt <palmer@...belt.com>, Paul
Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [RFC 3/3] riscv: dts: starfive: Add VisionFive 2 Lite board
device tree
> On 24.08.25 03:33, E Shattow wrote:
> On 8/21/25 03:09, Hal Feng wrote:
> > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
> >
> > Board features:
> > - JH7110S SoC
> > - 2/4/8 GiB LPDDR4 DRAM
> > - AXP15060 PMIC
> > - 40 pin GPIO header
> > - 1x USB 3.0 host port
> > - 3x USB 2.0 host port
> > - 1x M.2 M-Key (size: 2242)
> > - 1x MicroSD slot (optional non-removable eMMC)
> > - 1x QSPI Flash
> > - 1x I2C EEPROM
> > - 1x 1Gbps Ethernet port
> > - SDIO-based Wi-Fi & UART-based Bluetooth
> > - 1x HDMI port
> > - 1x 2-lane DSI
> > - 1x 2-lane CSI
> >
> > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/Makefile | 2 +
> > .../jh7110s-starfive-visionfive-2-lite.dts | 152 ++++++++++++++++++
> > 2 files changed, 154 insertions(+)
> > create mode 100644
> > arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> >
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > b/arch/riscv/boot/dts/starfive/Makefile
> > index b3bb12f78e7d..7265c363e2a9 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -13,3 +13,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-
> mars.dtb
> > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
> > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> > +
> > +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> > b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> > new file mode 100644
> > index 000000000000..a0cb9912eb80
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.
> > +++ dts
> > @@ -0,0 +1,152 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2025 Hal Feng <hal.feng@...rfivetech.com> */
> > +
> > +/dts-v1/;
> > +#include "jh7110-common.dtsi"
> > +
> > +/ {
> > + model = "StarFive VisionFive 2 Lite";
> > + compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; };
> > +
> > +&cpu_opp {
> > + opp-312500000 {
> > + opp-hz = /bits/ 64 <312500000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-417000000 {
> > + opp-hz = /bits/ 64 <417000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-625000000 {
> > + opp-hz = /bits/ 64 <625000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1250000000 {
> > + opp-hz = /bits/ 64 <1250000000>;
> > + opp-microvolt = <1000000>;
> > + };
> > +};
> > +
> > +&gmac0 {
> > + starfive,tx-use-rgmii-clk;
> > + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> > + assigned-clock-parents = <&aoncrg
> JH7110_AONCLK_GMAC0_RMII_RTX>;
> > + status = "okay";
> > +};
> > +
> > +&i2c0 {
> > + status = "okay";
> > +};
> > +
> > +&mmc0 {
> > + bus-width = <4>;
> > + no-sdio;
> > + no-mmc;
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
> > + disable-wp;
> > + cap-sd-highspeed;
> > +};
> > +
> > +&mmc1 {
> > + max-frequency = <50000000>;
> > + keep-power-in-suspend;
> > + non-removable;
> > +};
> > +
> > +&pcie1 {
> > + enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> > + status = "okay";
> > +};
> > +
> > +&phy0 {
> > + motorcomm,tx-clk-adj-enabled;
> > + motorcomm,tx-clk-100-inverted;
> > + motorcomm,tx-clk-1000-inverted;
> > + motorcomm,rx-clk-drv-microamp = <3970>;
> > + motorcomm,rx-data-drv-microamp = <2910>;
> > + rx-internal-delay-ps = <1500>;
> > + tx-internal-delay-ps = <1500>;
> > +};
> > +
> > +&pwm {
> > + status = "okay";
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > +};
> > +
> > +&syscrg {
> > + assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>,
> > +<1250000000>; };
>
> Circling back to a topic where I don't understand CPU clocks in hardware
> design, but I have questions, I would want to see 8 divisions instead of
> 4 divisions (for both JH7110S and for JH7110). Similar for JH7110S here as:
>
> &syscrg {
> assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>,
> <2500000000>; };
>
> and then in above &cpu_opp as:
>
> &cpu_opp {
> opp-312500000 {
> opp-hz = /bits/ 64 <312500000>;
> opp-microvolt = <800000>;
> };
> opp-357000000 {
> opp-hz = /bits/ 64 <357000000>;
> opp-microvolt = <800000>;
> };
> opp-417000000 {
> opp-hz = /bits/ 64 <417000000>;
> opp-microvolt = <800000>;
> };
> opp-500000000 {
> opp-hz = /bits/ 64 <500000000>;
> opp-microvolt = <800000>;
> };
> opp-625000000 {
> opp-hz = /bits/ 64 <625000000>;
> opp-microvolt = <800000>;
> };
> opp-833000000 {
> opp-hz = /bits/ 64 <833000000>;
> opp-microvolt = <800000>;
> };
> opp-1250000000 {
> opp-hz = /bits/ 64 <1250000000>;
> opp-microvolt = <1000000>;
> };
>
> /* avoid division=1 2.5GHz omitted here, not supported by CPU */ };
>
> What prevents this functionality I am asking about? Specifically on
> JH7110 the promotional block diagrams show 3.0GHz maximum (? I think?
> not sure but what else could this be?) so if that is true why do we not divide
> down from that, avoiding divisions that are problematic?
It is a good idea and I tested your code successfully on VF2 Lite.
But we have not done stress tests for this and I am not sure whether it will break the chip stability.
Anyway, it is a good suggestion and more tests should be run later.
Best regards,
Hal
> > +
> > +&sysgpio {
> > + uart1_pins: uart1-0 {
> > + tx-pins {
> > + pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-disable;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +
> > + rx-pins {
> > + pinmux = <GPIOMUX(23, GPOUT_LOW,
> > + GPOEN_DISABLE,
> > + GPI_SYS_UART1_RX)>;
> > + bias-pull-up;
> > + drive-strength = <2>;
> > + input-enable;
> > + input-schmitt-enable;
> > + slew-rate = <0>;
> > + };
> > +
> > + cts-pins {
> > + pinmux = <GPIOMUX(24, GPOUT_LOW,
> > + GPOEN_DISABLE,
> > + GPI_SYS_UART1_CTS)>;
> > + input-enable;
> > + };
> > +
> > + rts-pins {
> > + pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + input-enable;
> > + };
> > + };
> > +
> > + usb0_pins: usb0-0 {
> > + power-pins {
> > + pinmux = <GPIOMUX(26, GPOUT_HIGH,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + input-disable;
> > + };
> > + };
> > +};
> > +
> > +&uart1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart1_pins>;
> > + status = "okay";
> > +};
> > +
> > +&usb0 {
> > + dr_mode = "host";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&usb0_pins>;
> > + status = "okay";
> > +};
> > +
> > +&usb_cdns3 {
> > + phys = <&usbphy0>, <&pciephy0>;
> > + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; };
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